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    • 1. 发明授权
    • Error correction using reliability values for data matrix
    • 使用数据矩阵的可靠性值进行误差校正
    • US06434719B1
    • 2002-08-13
    • US09307282
    • 1999-05-07
    • Jay Neil Livingston
    • Jay Neil Livingston
    • G06F1100
    • G11B20/1833G11B20/10009G11B20/10064G11B20/10074
    • Erroneous column(s) in the matrix of data obtained from a transmission channel are first determined on the basis of column parity violation. An error instance in the matrix is next ascertained by matching the erroneous column(s) with an error event characteristic of the transmission channel. A candidate error row is then located in the matrix with respect to the error instance. Lastly, positions in the matrix specified by an intersection of the candidate error row and the erroneous column(s) of the error instance are corrected. Data reliability values assigned to positions of the matrix are used to determine the candidate error row. In particular, with respect to the erroneous column(s) of the error instance, and for each of plural rows of the matrix, factors (e.g., squares) of the reliability values assigned to positions of the matrix are summed to determine a least reliable row as the candidate error row. The operation of the invention is preferably preceded by a row error detection/correction operation which corrects single bit and tri-bit row errors in the matrix.
    • 从传输通道获得的数据矩阵中的错误列首先基于列奇偶校验违例确定。 接下来通过将错误列与传输信道的错误事件特性匹配来确定矩阵中的错误实例。 然后,相对于错误实例,候选错误行位于矩阵中。 最后,校正由候选错误行和错误实例的错误列的交点指定的矩阵中的位置。 使用分配给矩阵位置的数据可靠性值来确定候选错误行。 特别地,对于错误实例的错误列,并且对于矩阵的多行中的每一行,分配给矩阵的位置的可靠性值的因子(例如,正方形)相加以确定最不可靠 行作为候选错误行。 本发明的操作优选地在纠错矩阵中的单位和三位行错误的行错误检测/校正操作之前。
    • 3. 发明授权
    • Disk drive adapting equalizer relative to bit error rate of sequence detector
    • 磁盘驱动器适应均衡器相对于序列检测器的误码率
    • US07944639B1
    • 2011-05-17
    • US12178430
    • 2008-07-23
    • Alvin J. Wang
    • Alvin J. Wang
    • G11B5/53G11B5/09
    • G11B20/10009G11B20/10046G11B20/10064G11B20/10074G11B20/10175G11B20/10296G11B20/10379G11B20/10462G11B20/10509G11B2220/2516
    • A disk drive is disclosed comprising a disk and a head actuated radially over the disk, wherein the head generates a read signal. A sampling device samples the read signal to generate a sequence of read signal samples, and an equalizer comprising a plurality of coefficients, equalizes the read signal samples to generate a sequence of equalized samples. A sequence detector detects an estimated data sequence from the equalized samples, wherein the sequence detector operates according to a target response comprising a plurality of target values. Control circuitry adapts the equalizer coefficients by computing error values in response to a difference between expected samples and the equalized samples, computing a gradient in response to a correlation of the read signal samples with the error values, and adjusting at least one of the equalizer coefficients in response to the gradient.
    • 公开了一种磁盘驱动器,包括盘和径向地在盘上致动的磁头,其中磁头产生读取信号。 采样设备对读取信号进行采样以产生读取信号采样序列,并且包括多个系数的均衡器对均衡的采样信号进行均衡以产生均衡采样序列。 序列检测器从均衡样本检测估计数据序列,其中序列检测器根据包括多个目标值的目标响应进行操作。 控制电路通过响应于预期样本和均衡样本之间的差计算误差值来适应均衡器系数,响应于读取信号样本与误差值的相关性计算梯度,以及调整均衡器系数中的至少一个 响应梯度。
    • 5. 发明授权
    • Parity channel code for enhancing the operation of a remod/demod
sequence detector in a d=1 sampled amplitude read channel
    • 奇偶信道码,用于增强d = 1采样幅度读信道中的重索/解调序列检测器的操作
    • US6052248A
    • 2000-04-18
    • US16004
    • 1998-01-30
    • David E. ReedWilliam G. Bliss
    • David E. ReedWilliam G. Bliss
    • G11B20/10G11B5/09
    • G11B20/1403G11B20/10009G11B20/10037G11B20/10055G11B20/10064
    • A sampled amplitude read channel is disclosed for disk storage systems employing a run-length limited (RLL) d=1 channel code which compensates for partial erasure, and a parity channel code for enhancing the operation of a remod/demod sequence detector. During a write operation, after encoding the user data into codewords comprising the RLL d=1 constraint, the parity over one interleave of a block of NRZI bits is computed and two parity bits appended to form a parity codeword. For an even number of "1" bits in the block, the parity bits are set to "00". For an odd number of "1" bits in the block, the parity bits are set to "10" if the codeword ends with a "0" bit and to "01" if the codeword ends with a "1" bit, thereby maintaining the RLL d=1 constraint. Thus, a parity codeword will always comprise an even number of "1" bits (even parity). During read back, a parity syndrome is generated over a detected parity codeword; if the parity syndrome indicates the codeword comprises an odd number of "1" bits (odd parity), then the codeword is corrected according to the most likely error made by the remod/demod sequence detector. As a result, the remod/demod sequence detector of the present invention approaches the distance enhanced performance of matching a trellis state machine to the parity constraint, but with significantly less circuitry.
    • 对采用补偿部分擦除的游程限制(RLL)d = 1信道码的磁盘存储系统和用于增强重构/解调序列检测器的操作的奇偶校验信道码,公开了采样幅度读取信道。 在写操作期间,在将用户数据编码成包括RLL d = 1约束的码字之后,计算NRZI比特块的一个交织上的奇偶校验,并且附加两个奇偶校验位以形成奇偶码字。 对于块中的偶数“1”位,奇偶校验位设置为“00”。 对于块中的奇数“1”位,如果代码字以“1”位结束,则如果码字以“0”位结束,则奇偶校验位被设置为“10”,从而保持 RLL d = 1约束。 因此,奇偶码字将总是包括偶数“1”比特(偶校验)。 在回读期间,在检测到的奇偶码字上产生奇偶校验; 如果奇偶校验子码表示码字包括奇数“1”比特(奇校验),则根据由重构/解调序列检测器做出的最可能的错误来校正码字。 结果,本发明的重构/解调序列检测器接近将网格状态机匹配到奇偶校验约束的距离增强性能,但是具有显着更少的电路。
    • 6. 发明授权
    • Equalization for sample value estimation and sequence detection in a
sampled amplitude read channel
    • 采样幅度读取通道中采样值估计和序列检测的均衡
    • US5585975A
    • 1996-12-17
    • US340993
    • 1994-11-17
    • William G. Bliss
    • William G. Bliss
    • G11B20/10G11B5/09G11B5/035
    • G11B20/10055G11B20/10009G11B20/10037G11B20/10064G11B20/10074
    • In a sampled amplitude magnetic read channel, pulses in an analog signal corresponding to flux transitions on a magnetic medium are sampled and equalized into a first equalization for estimating sample values and into a second equalization for sequence detection of digital data. A gain and phase error detector generate respective error signals corresponding to the difference between estimated and actual sample values. Gain control and timing recovery use the error signals to adjust the amplitude and sampling frequency/phase of the analog read signal. A pair of programmable discrete time filters equalize the signal samples into the desired equalization. In a first embodiment, the signal samples are equalized to PR4 for estimating sample values and to EPR4 for sequence detection. A slicer processes the PR4 equalized sample values to generate the estimated sample values. The gain and phase error detectors generate the corresponding error signals according to a minimum mean squared error stochastic gradient algorithm. In a second embodiment, the signal samples are equalized to EPR4 for estimating sample values and to EEPR4 for sequence detection. A pulse detector processes the EPR4 equalized sample values in order to detect pulses in the analog signal and generate a corresponding pulse detect signal. The gain and phase error detectors generate the corresponding error signals in response to the pulse detect signal. To minimize circuitry and associated cost, the discrete time equalizing filters are implemented in series. For d=1 recording, the second equalizing filter is a (1+D) notch filter that attenuates the noise caused by clocking the discrete time circuitry at half the sampling rate, thereby increasing the accuracy of the sequence detector.
    • 在采样振幅磁读取通道中,对应于磁介质上的磁通转换的模拟信号中的脉冲被采样并均衡为用于估计采样值的第一均衡和用于数字数据的序列检测的第二均衡。 增益和相位误差检测器产生对应于估计和实际采样值之差的各个误差信号。 增益控制和定时恢复使用误差信号来调整模拟读取信号的幅度和采样频率/相位。 一对可编程离散时间滤波器将信号样本均衡到所需的均衡。 在第一实施例中,信号样本被均衡为PR4以估计样本值,并且将EPR4用于序列检测。 切片机处理PR4均衡样本值以生成估计的样本值。 增益和相位误差检测器根据最小均方误差随机梯度算法产生相应的误差信号。 在第二实施例中,将信号样本与用于估计采样值的EPR4相等,并将EEPR4与序列检测相等。 脉冲检测器处理EPR4均衡的采样值,以便检测模拟信号中的脉冲并产生相应的脉冲检测信号。 增益和相位误差检测器根据脉冲检测信号产生相应的误差信号。 为了最小化电路和相关成本,离散时间均衡滤波器被串联实现。 对于d = 1记录,第二均衡滤波器是(1 + D)陷波滤波器,其衰减以采样率的一半对离散时间电路计时引起的噪声,从而提高了序列检测器的精度。