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1. 发明授权

US09741864B2 Thin-film transistor and method for manufacturing same 有权
公开(公告)号：US09741864B2
公开(公告)日：2017-08-22
申请号：US14889919
申请日：2014-05-02
申请人： National Institute for Materials Science
发明人： Toshihide Nabatame , Kazuhito Tsukagoshi , Shinya Aikawa
IPC分类号： H01L29/78 , H01L29/786 , H01L29/66 , H01L21/02 , H01L21/40 , H01L29/423 , H01L29/49 , H01L29/51
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/40 , H01L29/42356 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/66969 , H01L29/78609 , H01L29/78693
摘要： The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method of manufacturing the same. The present invention provides a thin-film transistor provided with a source electrode (108), a drain electrode (109), a semiconductor layer (105), a gate electrode (103), and an insulating layer (104); wherein the semiconductor layer (105) contains a composite metal oxide obtained by adding to a first metal oxide an oxide having an oxygen dissociation energy that is at least 200 kJ/mol greater than the oxygen dissociation energy of the first metal oxide, whereby the amount of oxygen vacancy is controlled; and the insulating layer (104) is provided with an SiO2 layer, a high-permittivity first layer, and a high-permittivity second layer, whereby the dipoles generated at the boundary between the SiO2 layer and the high-permittivity layers are used to control the threshold voltage.

2. 发明授权

US08828794B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08828794B2
公开(公告)日：2014-09-09
申请号：US13413684
申请日：2012-03-07
申请人： Shunpei Yamazaki , Yuhei Sato , Keiji Sato , Tetsunori Maruyama , Junichi Koezuka
发明人： Shunpei Yamazaki , Yuhei Sato , Keiji Sato , Tetsunori Maruyama , Junichi Koezuka
IPC分类号： H01L21/42 , H01L21/84 , H01L21/336 , H01L27/12 , H01L29/786
CPC分类号： H01L21/40 , H01L21/02175 , H01L21/02252 , H01L21/02565 , H01L21/02636 , H01L21/02664 , H01L21/324 , H01L21/383 , H01L21/477 , H01L27/1225 , H01L29/66742 , H01L29/66969 , H01L29/7869
摘要： In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.
摘要翻译：在包括氧化物半导体膜的晶体管的制造过程中，对氧化物半导体膜进行氧掺杂处理，然后对氧化物半导体膜和设置在氧化物半导体膜上的氧化铝膜进行热处理。因此，形成包含比化学计量组成物多的氧的区域的氧化物半导体膜。使用氧化物半导体膜形成的晶体管可以具有高的可靠性，因为通过偏压 - 温度应力测试（BT测试）的晶体管的阈值电压的变化量减小。

3. 发明申请

US20100055462A1 Doped Nanocrystals 有权
标题翻译：掺杂的纳米晶体
公开(公告)号：US20100055462A1
公开(公告)日：2010-03-04
申请号：US12376371
申请日：2007-08-30
申请人： Y. Charles Cao
发明人： Y. Charles Cao
IPC分类号： B82B1/00 , B82B3/00
CPC分类号： H01L21/0257 , C09K11/02 , C09K11/565 , C09K11/574 , H01L21/02521 , H01L21/02601 , H01L21/242 , H01L21/40 , H01L29/225 , Y10T428/2991
摘要： A doping method using a three-step synthesis to make high-quality doped nanocrystals is provided. The first step includes synthesizing starting host particles. The second step includes dopant growth on the starting host particles. The third step includes final shell growth. In one embodiment, this method can be used to form Mn-doped CdS/ZnS core/shell nanocrystals. The Mn dopant can be formed inside the CdS core, at the core/shell interface, and/or in the ZnS shell. The subject method allows precisely controlling the impurity radial position and doping level in the nanocrystals.
摘要翻译：提供了使用三步合成制造高品质掺杂纳米晶体的掺杂方法。第一步包括合成起始的主体颗粒。第二步包括在起始主体颗粒上的掺杂剂生长。第三步包括最终的壳增长。在一个实施方案中，该方法可用于形成Mn掺杂的CdS / ZnS核/壳纳米晶体。 Mn掺杂剂可以形成在CdS芯内，核/壳界面和/或ZnS壳内。本方法允许精确控制纳米晶体中的杂质径向位置和掺杂水平。

4. 发明申请

US20180277392A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180277392A1
公开(公告)日：2018-09-27
申请号：US15991080
申请日：2018-05-29
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei YAMAZAKI , Yuhei SATO , Keiji SATO , Tetsunori MARUYAMA , Junichi KOEZUKA
IPC分类号： H01L21/40 , H01L21/324 , H01L29/66 , H01L21/02 , H01L29/786 , H01L21/383 , H01L21/477 , H01L27/12
CPC分类号： H01L21/40 , H01L21/02175 , H01L21/02252 , H01L21/02565 , H01L21/02636 , H01L21/02664 , H01L21/324 , H01L21/383 , H01L21/477 , H01L27/1225 , H01L29/66742 , H01L29/66969 , H01L29/7869
摘要： In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.

5. 发明申请

US20160365455A1 Thin-Film Transistor and Method for Manufacturing Same 审中-公开
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20160365455A1
公开(公告)日：2016-12-15
申请号：US15248567
申请日：2016-08-26
申请人： National Institute for Materials Science
发明人： Toshihide Nabatame , Kazuhito Tsukagoshi , Shinya Aikawa , Toyohiro Chikyo
IPC分类号： H01L29/786 , H01L29/66 , H01L29/423 , H01L29/49 , H01L29/51
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/40 , H01L29/42356 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/66969 , H01L29/78609 , H01L29/78693
摘要： The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method of manufacturing the same. The present invention provides a thin-film transistor provided with a source electrode (108), a drain electrode (109), a semiconductor layer (105), a gate electrode (103), and an insulating layer (104); wherein the semiconductor layer (105) contains a composite metal oxide obtained by adding to a first metal oxide an oxide having an oxygen dissociation energy that is at least 200 kJ/mol greater than the oxygen dissociation energy of the first metal oxide, whereby the amount of oxygen vacancy is controlled; and the insulating layer (104) is provided with an SiO2 layer, a high-permittivity first layer, and a high-permittivity second layer, whereby the dipoles generated at the boundary between the SiO2 layer and the high-permittivity layers are used to control the threshold voltage.
摘要翻译：本发明提供一种薄膜晶体管及其制造方法，其中诸如漏极电流和阈值电压的晶体管特性得到改善。本发明提供一种具有源电极（108），漏电极（109），半导体层（105），栅电极（103）和绝缘层（104）的薄膜晶体管。其中，所述半导体层（105）含有复合金属氧化物，所述复合金属氧化物通过向第一金属氧化物中添加比所述第一金属氧化物的氧解离能大至少200kJ / mol的氧解离能的氧化物而得到，的氧空位被控制; 并且绝缘层（104）设置有SiO 2层，高介电常数第一层和高电容率第二层，由此在SiO 2层和高介电常数层之间的边界处产生的偶极子用于控制阈值电压。

6. 发明申请

US20160351387A1 METHODS FOR FORMING NANOCRYSTALS WITH POSITION-CONTROLLED DOPANTS 审中-公开
标题翻译：用位置控制的二聚体形成纳米晶的方法
公开(公告)号：US20160351387A1
公开(公告)日：2016-12-01
申请号：US15200737
申请日：2016-07-01
申请人： University of Florida Research Foundation, Incorporated
发明人： Y. Charles Cao
IPC分类号： H01L21/02 , C09K11/57
CPC分类号： H01L21/0257 , C09K11/02 , C09K11/565 , C09K11/574 , H01L21/02521 , H01L21/02601 , H01L21/242 , H01L21/40 , H01L29/225 , Y10T428/2991
摘要： A doping method using a three-step synthesis to make high-quality doped nanocrystals is provided. The first step includes synthesizing starting host particles. The second step includes dopant growth on the starting host particles. The third step includes final shell growth. In one embodiment, this method can be used to form Mn-doped CdS/ZnS core/shell nanocrystals. The Mn dopant can be formed inside the CdS core, at the core/shell interface, and/or in the ZnS shell. The subject method allows precisely controlling the impurity radial position and doping level in the nanocrystals.
摘要翻译：提供了使用三步合成制造高品质掺杂纳米晶体的掺杂方法。第一步包括合成起始的主体颗粒。第二步包括在起始主体颗粒上的掺杂剂生长。第三步包括最终的壳增长。在一个实施方案中，该方法可用于形成Mn掺杂的CdS / ZnS核/壳纳米晶体。 Mn掺杂剂可以形成在CdS芯内，核/壳界面和/或ZnS壳内。本方法允许精确控制纳米晶体中的杂质径向位置和掺杂水平。

7. 发明授权

US4520382A Semiconductor integrated circuit with inversion preventing electrode 失效
标题翻译：具有防反转电极的半导体集成电路
公开(公告)号：US4520382A
公开(公告)日：1985-05-28
申请号：US303134
申请日：1981-09-17
申请人： Tastuo Shimura
发明人： Tastuo Shimura
IPC分类号： H01L29/78 , H01L21/40 , H01L21/76 , H01L21/762 , H01L29/40 , H01L29/41 , H01L29/74 , H01L25/04 , H01L27/04 , H01L27/12
CPC分类号： H01L21/40 , H01L21/76297
摘要： A semiconductor monolithic integrated circuit device in which leakage current is decreased. An island region of a first conductivity type formed in a semiconductor chip has at least two diffused regions of a second conductivity type opposite to the first conductivity type. An insulation film is deposited on the island region. The island region and the diffused regions are contacted with respective electrodes with low resistances through openings formed in the insulation film. An inversion stopping electrode is provided for and connected to the electrode of at least one of the diffused regions. The inversion stopping electrode is so disposed as to enclose the one diffused region against the other diffused region in cooperation with the boundary of the island region as viewed in a plane of the semiconductor chip. Upon application of a voltage, a depletion layer or inversion layer extending from the other diffused region terminates at a position immediately below the inversion stopping electrode, whereby possibility of leakage current flowing through the inversion layer is reduced.
摘要翻译：泄漏电流降低的半导体单片集成电路器件。形成在半导体芯片中的第一导电类型的岛区域具有与第一导电类型相反的至少两个第二导电类型的扩散区域。绝缘膜沉积在岛状区域上。岛状区域和扩散区域通过形成在绝缘膜中的开口的低电阻与各个电极接触。为至少一个扩散区域的电极设置并连接到反向停止电极。反转停止电极被配置为在半导体芯片的平面中观察时与岛区域的边界协调地将一个扩散区域封闭在另一个扩散区域上。在施加电压时，从另一个扩散区延伸的耗尽层或反转层终止于反转停止电极正下方的位置，由此流过反型层的漏电流的可能性降低。

8. 发明授权

US10002775B2 Method of manufacturing semiconductor device 有权
公开(公告)号：US10002775B2
公开(公告)日：2018-06-19
申请号：US15169925
申请日：2016-06-01
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki , Yuhei Sato , Keiji Sato , Tetsunori Maruyama , Junichi Koezuka
IPC分类号： H01L21/40 , H01L21/383 , H01L21/477 , H01L21/02 , H01L29/66 , H01L29/786 , H01L27/12 , H01L21/324
CPC分类号： H01L21/40 , H01L21/02175 , H01L21/02252 , H01L21/02565 , H01L21/02636 , H01L21/02664 , H01L21/324 , H01L21/383 , H01L21/477 , H01L27/1225 , H01L29/66742 , H01L29/66969 , H01L29/7869
摘要： In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.

9. 发明申请

US20120231580A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120231580A1
公开(公告)日：2012-09-13
申请号：US13413684
申请日：2012-03-07
申请人： Shunpei YAMAZAKI , Yuhei SATO , Keiji SATO , Tetsunori MARUYAMA , Junichi KOEZUKA
发明人： Shunpei YAMAZAKI , Yuhei SATO , Keiji SATO , Tetsunori MARUYAMA , Junichi KOEZUKA
IPC分类号： H01L21/42
CPC分类号： H01L21/40 , H01L21/02175 , H01L21/02252 , H01L21/02565 , H01L21/02636 , H01L21/02664 , H01L21/324 , H01L21/383 , H01L21/477 , H01L27/1225 , H01L29/66742 , H01L29/66969 , H01L29/7869
摘要： In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.
摘要翻译：在包括氧化物半导体膜的晶体管的制造过程中，对氧化物半导体膜进行氧掺杂处理，然后对氧化物半导体膜和设置在氧化物半导体膜上的氧化铝膜进行热处理。因此，形成包含比化学计量组成物多的氧的区域的氧化物半导体膜。使用氧化物半导体膜形成的晶体管可以具有高的可靠性，因为通过偏压 - 温度应力测试（BT测试）的晶体管的阈值电压的变化量减小。

10. 发明授权

US5767536A II-VI group compound semiconductor device 失效
标题翻译： II-VI族化合物半导体器件
公开(公告)号：US5767536A
公开(公告)日：1998-06-16
申请号：US756192
申请日：1996-11-25
申请人： Masanori Murakami , Yasuo Koide , Nobuaki Teraguchi , Yoshitaka Tomomura
发明人： Masanori Murakami , Yasuo Koide , Nobuaki Teraguchi , Yoshitaka Tomomura
IPC分类号： H01L21/28 , H01L21/363 , H01L21/40 , H01L21/44 , H01L21/443 , H01L29/221 , H01L29/45 , H01L29/47 , H01L33/28 , H01L33/40 , H01S5/00 , H01L33/00
CPC分类号： H01L33/40 , H01L21/40 , H01L21/44 , H01L21/443 , H01L29/221 , H01L29/45 , H01L29/47 , H01L33/28
摘要： A II-VI group compound semiconductor device comprising a Zn.sub.X Mg.sub.1-X S.sub.Y Se.sub.1-Y (0.ltoreq.X.ltoreq.1, 0.ltoreq.Y.ltoreq.1) semiconductor layer, an intermediate layer comprising a compound of an element constituting the semiconductor layer and an additive element of Cd, Te or Hg formed on the semiconductor layer, and an electrode layer containing Ni, Pt or Pd formed on the intermediate layer.
摘要翻译：包含ZnXMg1-XSYSe1-Y（0≤x≤1,0≤Y≤1）半导体层的II-VI族化合物半导体器件，包含构成该化合物的元素的化合物的中间层半导体层和形成在半导体层上的Cd，Te或Hg的添加元素，以及形成在中间层上的含有Ni，Pt或Pd的电极层。

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