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1. 发明申请

US20180254212A1 Interconnect Structure That Avoids Insulating Layer Damage and Methods of Making the Same 审中-公开
公开(公告)号：US20180254212A1
公开(公告)日：2018-09-06
申请号：US15970596
申请日：2018-05-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Bo-Jiun Lin , Hai-Ching Chen , Tien-I Bao
IPC分类号： H01L21/768 , H01L23/532 , H01L21/02
CPC分类号： H01L21/7685 , C23C18/1216 , C23C18/1254 , C23C18/1295 , C23C18/14 , C23C30/00 , C25D3/38 , H01L21/02178 , H01L21/022 , H01L21/02282 , H01L21/02304 , H01L21/2885 , H01L21/76807 , H01L21/76811 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/7684 , H01L21/76862 , H01L21/76877 , H01L21/76883 , H01L23/5283 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2221/1015 , H01L2221/1021 , H01L2221/1073 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure includes forming an insulating layer on a substrate. A damascene opening is formed through a thickness portion of the insulating layer. A diffusion barrier layer is formed to line the damascene opening. A conductive layer is formed overlying the diffusion barrier layer to fill the damascene opening. A carbon-containing metal oxide layer is formed on the conductive layer and the insulating layer.

2. 发明申请

US20180040510A1 SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA 审中-公开
公开(公告)号：US20180040510A1
公开(公告)日：2018-02-08
申请号：US15229470
申请日：2016-08-05
申请人： International Business Machines Corporation
发明人： Benjamin D. Briggs , Jessica Dechene , Elbert E. Huang , Joe Lee , Theodorus E. Standaert
IPC分类号： H01L21/768 , H01L23/532 , H01L23/522
CPC分类号： H01L21/76897 , H01L21/7681 , H01L21/76834 , H01L21/7684 , H01L23/5226 , H01L23/5283 , H01L23/53228 , H01L23/5329 , H01L2221/1021
摘要： A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

3. 发明授权

US09040417B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09040417B2
公开(公告)日：2015-05-26
申请号：US14046516
申请日：2013-10-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hsin-Chieh Yao , Chung-Ju Lee , Tien-I Bao , Shau-Lin Shue
IPC分类号： H01L21/44 , H01L23/522 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/31144 , H01L21/76802 , H01L21/76808 , H01L21/7681 , H01L21/76823 , H01L21/76832 , H01L21/76834 , H01L23/522 , H01L23/5226 , H01L23/53228 , H01L23/53233 , H01L23/53295 , H01L2221/1021 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an insulating material layer over a workpiece, patterning an upper portion of the insulating material layer with a conductive line pattern, and forming a stop layer comprising a metal oxide or a metal nitride over the patterned insulating material layer. A masking material is formed over the stop layer, and the masking material is patterned with a via pattern. The via pattern of the masking material is transferred to a lower portion of the insulating material layer.
摘要翻译：公开了半导体器件及其制造方法。在一些实施例中，制造半导体器件的方法包括在工件上形成绝缘材料层，以导电图案图案化绝缘材料层的上部，并且形成包含金属氧化物或金属氮化物的停止层图案化的绝缘材料层。在停止层上形成掩模材料，并且用通孔图案对掩模材料进行图案化。掩模材料的通孔图案被转移到绝缘材料层的下部。

4. 发明申请

US20130178068A1 DUAL DAMASCENE PROCESS AND APPARATUS 审中-公开
标题翻译：双重加工工艺和设备
公开(公告)号：US20130178068A1
公开(公告)日：2013-07-11
申请号：US13346781
申请日：2012-01-10
申请人： Chai Der YEN , Fu-Cheng CHANG , Cheng-Pang YEH , Hung-Yu CHIU , Hung-Che LIAO
发明人： Chai Der YEN , Fu-Cheng CHANG , Cheng-Pang YEH , Hung-Yu CHIU , Hung-Che LIAO
IPC分类号： H01L21/302 , G03F1/00
CPC分类号： H01L21/0274 , G03F1/50 , G03F1/54 , H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L2221/1021
摘要： A method comprising providing at least one dielectric layer above a semiconductor substrate, the at least one dielectric layer having a top surface and a bottom surface; forming a photoresist layer on the top surface of the at least one dielectric layer; providing a single photomask having at least one first pattern corresponding to a conductive via and at least one second pattern corresponding to a conductive trace; patterning the photoresist layer using the single photomask, for forming a trench in the photoresist corresponding to the conductive trace and an opening in a bottom surface of the trench corresponding to the via with a single photo exposure step; and etching the dielectric through the photoresist layer to form the trench and via therein. This application also relates to photomasks for use in the methods of this application.
摘要翻译：一种方法，包括在半导体衬底上提供至少一个电介质层，所述至少一个电介质层具有顶表面和底表面; 在所述至少一个介电层的顶表面上形成光致抗蚀剂层; 提供具有对应于导电通孔的至少一个第一图案和对应于导电迹线的至少一个第二图案的单个光掩模; 使用单个光掩模图案化光致抗蚀剂层，用于在对应于导电迹线的光致抗蚀剂中形成沟槽，并且通过单次曝光步骤在对应于通孔的沟槽的底表面中形成开口; 并通过光致抗蚀剂层蚀刻电介质以在其中形成沟槽和通孔。本申请还涉及用于本申请方法的光掩膜。

5. 发明申请

US20120115303A1 METHOD OF FABRICATING DAMASCENE STRUCTURES 有权
标题翻译：制备大分子结构的方法
公开(公告)号：US20120115303A1
公开(公告)日：2012-05-10
申请号：US13354371
申请日：2012-01-20
申请人： Jeffrey P. Gambino , Peter J. Lindgren , Anthony K. Stamper
发明人： Jeffrey P. Gambino , Peter J. Lindgren , Anthony K. Stamper
IPC分类号： H01L21/4763 , H01L21/02
CPC分类号： H01L21/76802 , H01L21/76807 , H01L23/5223 , H01L28/40 , H01L2221/1021 , H01L2221/1063
摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.
摘要翻译：在集成电路中形成导线的方法。所述方法包括在基板上的第一电介质层中形成导线; 在所述导线和所述第一介电层上形成介电阻挡层; 在阻挡层上形成第二电介质层; 在所述第二介电层上形成一个或多个图案化的光致抗蚀剂层; 执行反应离子蚀刻以蚀刻通过第二介电层而不穿过阻挡层的沟槽; 执行第二反应离子蚀刻以将沟槽延伸穿过阻挡层; 并且在执行第二反应离子蚀刻之后，去除一个或多个图案化的光致抗蚀剂层，使用还原等离子体或非氧化等离子体去除最后形成的图案化光致抗蚀剂层。所述方法包括通过与金属 - 绝缘体 - 金属电容器类似的方法形成导线。

6. 发明申请

US20110117723A1 NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO ALIGNMENT AND FEATURE SHAPING 有权
标题翻译： NANO印花技术与对准和特征形状相比具有更高的灵活性
公开(公告)号：US20110117723A1
公开(公告)日：2011-05-19
申请号：US13014771
申请日：2011-01-27
申请人： Robert Seidel , Carsten Peters , Frank Feustel
发明人： Robert Seidel , Carsten Peters , Frank Feustel
IPC分类号： H01L21/768 , H01L21/762 , H01L21/28
CPC分类号： B81B7/0006 , B81C2201/0153 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/28114 , H01L21/76224 , H01L21/76229 , H01L21/76804 , H01L21/76807 , H01L21/76817 , H01L21/76838 , H01L21/76852 , H01L21/76885 , H01L2221/1021
摘要： By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like.
摘要翻译：通过基于压印技术形成金属化结构，其中可以通常形成通孔和沟槽，由于根据常规工艺技术所要求的至少一个进一步对准过程，可以实现工艺复杂性的显着降低。此外，可以通过提供适当设计的压印模具来提高压印光刻的灵活性和效率，以便提供表现出增加的填充能力的通孔开口和沟槽，从而也提高了最终获得的金属化结构在可靠性，抗性电迁移等。

7. 发明申请

US20100311241A1 THREE-STATE MASK AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：三状态掩模和使用其制造半导体器件的方法
公开(公告)号：US20100311241A1
公开(公告)日：2010-12-09
申请号：US12565994
申请日：2009-09-24
申请人： Jae-Hyun Kang
发明人： Jae-Hyun Kang
IPC分类号： H01L21/768 , G03F1/00
CPC分类号： H01L21/31144 , G03F1/50 , H01L21/0274 , H01L21/76807 , H01L21/76808 , H01L2221/1021
摘要： A three-state mask, which is used during exposure of a lithography process and formed in a regular pattern, includes a first transmission region to transmit substantially all incident light, second transmission regions to transmit a portion of incident light, and shield regions to block transmission of light. Therefore, the three-state mask shortens two lithography processes into one lithography process, eliminates misalignment between a via hole and a trench, prevents lowering of a sheet resistance (Rs) due to misalignment, simplifies a dual damascene process, reduces the number of masks used in the dual damascene process, and thus contributes to reduction of manufacturing costs of the semiconductor device.
摘要翻译：在光刻处理曝光期间使用并以规则图案形成的三态掩模包括基本上透射所有入射光的第一透射区域，用于透射入射光的一部分的第二透射区域，以及屏蔽区域透光。因此，三态掩模将两个光刻工艺缩短成一个光刻工艺，消除通孔和沟槽之间的未对准，防止由于不对准而导致的薄层电阻（Rs）的降低，简化了双镶嵌工艺，减少了掩模的数量用于双镶嵌工艺，从而有助于降低半导体器件的制造成本。

8. 发明授权

US07446057B2 Fabrication method 失效
标题翻译：制作方法
公开(公告)号：US07446057B2
公开(公告)日：2008-11-04
申请号：US10574150
申请日：2004-08-23
申请人： Alexander Bietsch , Bruno Michel
发明人： Alexander Bietsch , Bruno Michel
IPC分类号： H01L21/20
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/76807 , H01L2221/1021 , Y10S438/946
摘要： A method for forming a multilevel structure on a surface by depositing a curable liquid layer on the surface; pressing a stamp having a multilevel pattern therein into the liquid layer to produce in the liquid layer a multilevel structure defined by the pattern; and, curing the liquid layer to produce a solid layer having the multilevel structure therein. Mechanical alignment may be employed to enhance optical alignment of the stamp relative to the substrate via spaced protrusions on the substrate on which the structure is to be formed and complementary recesses in the patterning of the stamp.
摘要翻译：一种通过在表面上沉积可固化液体层而在表面上形成多层结构的方法; 将其中具有多层图案的印模压入液体层中，以在液体层中产生由图案限定的多层结构; 并且固化液体层以产生其中具有多层结构的固体层。可以采用机械对准来增强印模相对于基板的光学对准，通过其上要形成结构的基板上的间隔开的突起和印模的图案化中的互补凹槽。

9. 发明申请

US20070275556A1 Fabrication Method 失效
标题翻译：制作方法
公开(公告)号：US20070275556A1
公开(公告)日：2007-11-29
申请号：US10574150
申请日：2004-08-23
申请人： Alexander Bietsch , Bruno Michel
发明人： Alexander Bietsch , Bruno Michel
IPC分类号： H01L21/4763
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/76807 , H01L2221/1021 , Y10S438/946
摘要： A method for forming a multilevel structure on a surface by depositing a curable liquid layer on the surface; pressing a stamp having a multilevel pattern therein into the liquid layer to produce in the liquid layer a multilevel structure defined by the pattern; and, curing the liquid layer to produce a solid layer having the multilevel structure therein. Mechanical alignment may be employed to enhance optical alignment of the stamp relative to the substrate via spaced protrusions on the substrate on which the structure is to be formed and complementary recesses in the patterning of the stamp.
摘要翻译：一种通过在表面上沉积可固化液体层而在表面上形成多层结构的方法; 将其中具有多层图案的印模压入液体层中，以在液体层中产生由图案限定的多层结构; 并且固化液体层以产生其中具有多层结构的固体层。可以采用机械对准来增强印模相对于基板的光学对准，通过其上要形成结构的基板上的间隔开的突起和印模的图案化中的互补凹槽。

10. 发明申请

US20030003716A1 Method for forming dual damascene line structure 失效
标题翻译：形成双镶嵌线结构的方法
公开(公告)号：US20030003716A1
公开(公告)日：2003-01-02
申请号：US10062716
申请日：2002-02-05
申请人： Hynix Semiconductor Inc.
发明人： Kil Ho Kim
IPC分类号： H01L021/336
CPC分类号： H01L21/76811 , H01L21/76813 , H01L2221/1021
摘要： A method for forming a dual damascene line structure includes forming an inter-metal dielectric including a first region and a second region on a semiconductor substrate, forming a first hard mask material layer on an entire surface of the inter-metal dielectric, removing the first hard mask material layer on the first region, forming a second hard mask material layer on an entire surface of the inter-metal dielectric, forming a hard mask to remove a portion of the first hard mask material layer on the second region, etching the inter-metal dielectric of the first region to a first thickness using the hard mask, exposing the inter-metal dielectric of the second region, and etching the exposed inter-metal dielectric to simultaneously form a via hole and a trench having the via hole.
摘要翻译：一种用于形成双镶嵌线结构的方法包括在半导体衬底上形成包括第一区域和第二区域的金属间电介质，在金属间电介质的整个表面上形成第一硬掩模材料层，在所述第一区域上形成硬掩模材料层，在所述金属间电介质的整个表面上形成第二硬掩模材料层，形成硬掩模以去除所述第二区域上的所述第一硬掩模材料层的一部分，使用所述硬掩模将所述第一区域的金属电介质施加到第一厚度，暴露所述第二区域的所述金属间电介质，以及蚀刻所暴露的金属间电介质以同时形成通孔和具有所述通孔的沟槽。

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