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1. 发明申请

US20180197915A1 INTEGRATED MAGNETIC TUNNEL JUNCTION (MTJ) IN BACK END OF LINE (BEOL) INTERCONNECTS 审中-公开
公开(公告)号：US20180197915A1
公开(公告)日：2018-07-12
申请号：US15824448
申请日：2017-11-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Benjamin D. Briggs , Michael Rizzolo , Theodorus E. Standaert
IPC分类号： H01L27/22 , H01L43/08 , H01L43/12 , H01L43/02 , H01L27/112 , H01L21/02 , H01L21/8239 , H01L21/8229 , H01L21/67 , H01L21/3213 , H01L21/311 , H01L21/306 , H01L21/04 , H01L43/10 , H01L27/105
CPC分类号： H01L27/222 , H01L21/02019 , H01L21/0475 , H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/67063 , H01L21/8229 , H01L21/8239 , H01L27/1052 , H01L27/112 , H01L27/11502 , H01L27/11585 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12 , H01L2924/1441
摘要： A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.

2. 发明申请

US20180122917A1 Transistors, Memory Cells and Semiconductor Constructions 审中-公开
公开(公告)号：US20180122917A1
公开(公告)日：2018-05-03
申请号：US15859122
申请日：2017-12-29
申请人： Micron Technology, Inc.
发明人： Durai Vishak Ramaswamy , Kirk D. Prall , Wayne Kinney
IPC分类号： H01L29/51 , H01L29/78 , H01L29/40 , H01L29/423 , H01L29/10 , H01L29/08 , H01L27/108
CPC分类号： H01L29/516 , G11C14/0027 , H01L27/10823 , H01L27/10876 , H01L27/11585 , H01L27/1159 , H01L29/0847 , H01L29/1037 , H01L29/40111 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/6684 , H01L29/78391 , H01L45/1206 , H01L45/1233 , H01L45/14
摘要： Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

3. 发明申请

US20180006129A1 TRANSISTOR AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20180006129A1
公开(公告)日：2018-01-04
申请号：US15628592
申请日：2017-06-20
申请人： UNITED MICROELECTRONICS CORP.
发明人： Su Xing , Hsueh-Wen Wang , Chien-Yu Ko , Yu-Cheng Tung , Jen-Yu Wang , Cheng-Tung Huang , Yu-Ming Lin
IPC分类号： H01L29/51 , H01L29/66 , H01L29/786
CPC分类号： H01L29/516 , H01L21/28291 , H01L27/11585 , H01L29/0649 , H01L29/4236 , H01L29/4908 , H01L29/66545 , H01L29/6684 , H01L29/66969 , H01L29/7869
摘要： A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.

4. 发明申请

US20170133478A1 Transistors, Memory Cells and Semiconductor Constructions 有权
公开(公告)号：US20170133478A1
公开(公告)日：2017-05-11
申请号：US15411886
申请日：2017-01-20
申请人： Micron Technology, Inc.
发明人： Durai Vishak Ramaswamy , Kirk D. Prall , Wayne Kinney
IPC分类号： H01L29/51 , H01L29/10 , H01L29/423 , H01L27/1159 , H01L29/40 , H01L29/78 , H01L29/08
CPC分类号： H01L29/516 , G11C14/0027 , H01L21/28291 , H01L27/10823 , H01L27/10876 , H01L27/11585 , H01L27/1159 , H01L29/0847 , H01L29/1037 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/6684 , H01L29/7827 , H01L29/78391 , H01L29/784 , H01L45/1206 , H01L45/1233 , H01L45/14
摘要： Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

5. 发明授权

US09559118B2 Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors 有权
标题翻译：垂直铁电场效应晶体管结构，包括一对垂直铁电场效应晶体管的结构，铁电场效应晶体管的垂直串和横向相对的垂直铁电场效应晶体管的垂直串
公开(公告)号：US09559118B2
公开(公告)日：2017-01-31
申请号：US15095211
申请日：2016-04-11
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , Chandra Mouli , Gurtej S. Sandhu
IPC分类号： H01L27/115 , H01L21/02 , H01L21/28 , H01L29/51 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/24 , H01L29/78 , G11C11/22
CPC分类号： H01L27/11597 , G11C11/22 , H01L21/02568 , H01L21/28291 , H01L27/11514 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L27/11585 , H01L27/1159 , H01L29/0649 , H01L29/1037 , H01L29/24 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/516 , H01L29/6684 , H01L29/7827 , H01L29/78642 , H01L29/78681 , H01L2029/42388
摘要： A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.
摘要翻译：垂直铁电场效应晶体管结构包括隔离芯。过渡金属二硫属元素材料环绕隔离芯并具有1个单层至7个单层的侧壁厚度。铁电栅极电介质材料围绕过渡金属二硫属元素材料。导电栅极材料围绕铁电栅极电介质材料。过渡金属二硫属元素材料在导电栅极材料的高度向内和向外向外延伸。导电接触件直接抵靠过渡金属二硫属化物材料的侧向外侧壁，其是导电栅极材料的顶部向内，或b）导电栅极材料的向外侧。公开了另外的实施例。

6. 发明申请

US20160071852A1 FERROELECTRIC MEMORY DEVICE 审中-公开
标题翻译：电磁存储器件
公开(公告)号：US20160071852A1
公开(公告)日：2016-03-10
申请号：US14785544
申请日：2014-04-16
申请人： ARKEMA FRANCE
发明人： Fabrice DOMINGUES DOS SANTOS , Thierry LANNUZEL
IPC分类号： H01L27/115 , H01L29/78 , H01L29/51 , H01L51/05
CPC分类号： H01L27/11507 , C08F214/22 , H01G4/14 , H01G4/18 , H01G4/33 , H01G7/06 , H01L21/28291 , H01L27/101 , H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L27/285 , H01L28/40 , H01L28/55 , H01L29/516 , H01L29/6684 , H01L29/78391 , H01L29/861 , H01L51/0034 , H01L51/004 , H01L51/0043 , H01L51/0575 , C08F214/26 , C08F214/18
摘要： The invention relates to a ferroelectric memory device comprising at least one layer comprising a ferroelectric polymer, and at least two electrodes either side thereof, the ferroelectric polymer being of general formula P(VDF-X-Y), wherein VDF is vinylidene fluoride motifs, X is trifluoroethylene or tetrafluoroethylene motifs, and Y is motifs from a third monomer, the molar proportion of Y motifs in the polymer being less than or equal to 6.5%.
摘要翻译：本发明涉及一种强电介质存储器件，其包括至少一层包含铁电聚合物和至少两个电极的两侧，铁电聚合物为通式P（VDF-XY），其中VDF为偏二氟乙烯基体，X为三氟乙烯或四氟乙烯基序，Y是来自第三单体的基序，Y基序在聚合物中的摩尔比例小于或等于6.5％。

7. 发明授权

US08796751B2 Transistors, memory cells and semiconductor constructions 有权
标题翻译：晶体管，存储单元和半导体结构
公开(公告)号：US08796751B2
公开(公告)日：2014-08-05
申请号：US13682190
申请日：2012-11-20
申请人： Micron Technology, Inc.
发明人： Nirmal Ramaswamy , Kirk D. Prall , Wayne Kinney
IPC分类号： H01L31/062
CPC分类号： H01L29/516 , G11C14/0027 , H01L21/28291 , H01L27/10823 , H01L27/10876 , H01L27/11585 , H01L27/1159 , H01L29/0847 , H01L29/1037 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/6684 , H01L29/7827 , H01L29/78391 , H01L29/784 , H01L45/1206 , H01L45/1233 , H01L45/14
摘要： Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.
摘要翻译：一些实施例包括具有延伸到半导体基底中的栅极的半导体结构。导电掺杂的源极和漏极区域在与栅极相邻的基极内。栅极电介质在源极区域和栅极之间具有第一区段，在漏极区域和栅极之间的第二区段以及第一和第二区段之间的第三区段。栅电介质的至少一部分包括铁电材料。在一些实施例中，铁电材料在第一，第二和第三段内。在一些实施例中，铁电材料在第一段或第三段内。在一些实施例中，晶体管具有栅极，源极区和漏极区; 并且在源区和漏区之间具有沟道区。晶体管具有在源极区域和栅极之间包含铁电材料的栅极电介质。

8. 发明申请

US20140138753A1 Transistors, Memory Cells and Semiconductor Constructions 有权
公开(公告)号：US20140138753A1
公开(公告)日：2014-05-22
申请号：US13682190
申请日：2012-11-20
申请人： MICRON TECHNOLOGY, INC.
发明人： Nirmal Ramaswamy , Kirk D. Prall , Wayne Kinney
IPC分类号： H01L29/78
CPC分类号： H01L29/516 , G11C14/0027 , H01L21/28291 , H01L27/10823 , H01L27/10876 , H01L27/11585 , H01L27/1159 , H01L29/0847 , H01L29/1037 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/6684 , H01L29/7827 , H01L29/78391 , H01L29/784 , H01L45/1206 , H01L45/1233 , H01L45/14
摘要： Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

9. 发明授权

US07898009B2 Independently-double-gated transistor memory (IDGM) 有权
标题翻译：独立双门控晶体管存储器（IDGM）
公开(公告)号：US07898009B2
公开(公告)日：2011-03-01
申请号：US11678026
申请日：2007-02-22
申请人： Dale G. Wilson , Kelly James DeGregorio , Stephen A. Parke , Douglas R. Hackler, Sr.
发明人： Dale G. Wilson , Kelly James DeGregorio , Stephen A. Parke , Douglas R. Hackler, Sr.
IPC分类号： H01L29/80
CPC分类号： H01L27/1203 , G11C11/22 , G11C11/223 , H01L27/11585
摘要： Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
摘要翻译：存储单元由具有独立门控制的双门控四端子晶体管构成。 DRAM单元可以使用一个，两个或三个晶体管。单晶体管单元被构造为具有或不具有位存储电容器，并且描述NAND和NOR型非易失性NVRAM单元以及铁电FeRAM单元。对于所有电池，顶门提供常规接入，而独立的底栅提供控制以优化给定速度和功率参数的存储器保持以及适应对辐射的硬化。在没有电容器的单个晶体管电池中，使用底部栅极可以将密封包装到接近2 F2的密度。使用铁电材料作为栅极绝缘体产生单晶体管FeRAM单元，其克服了行业范围的写入干扰问题。存储单元与SOI逻辑电路兼容，用作SOC应用中的嵌入式RAM。

10. 发明授权

US07759762B2 Semiconductor device formed on (111) surface of a Si crystal and fabrication process thereof 失效
公开(公告)号：US07759762B2
公开(公告)日：2010-07-20
申请号：US10986778
申请日：2004-11-15
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Katsuyuki Sekine , Yuji Saito
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Katsuyuki Sekine , Yuji Saito
IPC分类号： H01L29/00
CPC分类号： H01L21/28185 , G11C11/16 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28238 , H01L21/28291 , H01L27/11521 , H01L27/11585 , H01L27/1159 , H01L27/1203 , H01L29/045 , H01L29/4908 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/7833 , H01L29/78603 , H01L29/78612 , H01L29/7883
摘要： A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr.

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