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1. 发明授权

US09978865B2 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US09978865B2
公开(公告)日：2018-05-22
申请号：US15385060
申请日：2016-12-20
申请人： Samsung Electronics Co., Ltd.
发明人： Jae Hong Kwon , Youngho Lee , Hoon Lim , Hyungsoon Jang , Eunguk Chung
IPC分类号： H01L29/78 , H01L27/092 , H01L29/08 , H01L27/11 , H01L29/16 , H01L29/66
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L27/092 , H01L27/0924 , H01L27/1104 , H01L28/00 , H01L29/0852 , H01L29/1045 , H01L29/1083 , H01L29/1608 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

2. 发明授权

US09362394B2 Power device termination structures and methods 有权
标题翻译：功率器件端接结构和方法
公开(公告)号：US09362394B2
公开(公告)日：2016-06-07
申请号：US14307678
申请日：2014-06-18
申请人： Moaniss Zitouni , Edouard D. de Frésart , Pon Sung Ku , Ganming Qin
发明人： Moaniss Zitouni , Edouard D. de Frésart , Pon Sung Ku , Ganming Qin
IPC分类号： H01L29/78 , G06F17/50 , H01L29/66 , H01L29/06 , H01L29/40 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L29/7813 , G06F17/5009 , G06F17/5072 , H01L29/063 , H01L29/0696 , H01L29/0852 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.
摘要翻译：本文公开了功率器件端接结构和方法。该结构包括沟槽栅极半导体器件。沟槽栅极半导体器件包括半导体材料和沟槽栅极功率晶体管阵列。阵列限定包括多个内部晶体管的内部区域和包括多个外部晶体管的外部区域。内部晶体管包括具有平均内部区域间隔的多个内部沟槽。外部晶体管包括具有平均端接区域间隔的多个外部沟槽。平均端接区域间隔大于平均内部区域间隔，或者被选择为使得多个外部晶体管的击穿电压大于多个内部晶体管的击穿电压。

3. 发明申请

US20140327075A1 HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGES 审中-公开
标题翻译：具有增加的断电电压的高压和超高压半导体器件
公开(公告)号：US20140327075A1
公开(公告)日：2014-11-06
申请号：US14333886
申请日：2014-07-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ker Hsiao HUO , Ru-Yi SU , Fu-Chih YANG , Chun Lin TSAI , Chih-Chang CHENG
IPC分类号： H01L29/78 , H01L29/49
CPC分类号： H01L29/404 , H01L29/0607 , H01L29/0615 , H01L29/0649 , H01L29/0696 , H01L29/0852 , H01L29/0869 , H01L29/0886 , H01L29/1095 , H01L29/402 , H01L29/41758 , H01L29/4238 , H01L29/49 , H01L29/66674 , H01L29/66681 , H01L29/7801 , H01L29/7816
摘要： A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.
摘要翻译：横向DMOS晶体管设置有源极区，漏极区和导电栅。漏极区域通过在导电栅极下方侵入的场氧化物与导电栅极横向分离。横向DMOS晶体管可以形成为跑道状结构，其中导电栅极包括直线部分和弯曲部分并被源极区域包围。布置在导电栅极和捕获的漏极之间是一层或多层次的层间电介质材料。一组或多组隔离的导体引线形成在电介质层中或介质层上，并且可以设置在多个器件级。隔离导电引线增加了横向DMOS晶体管的击穿电压，特别是在电场拥挤可能会降低击穿电压的弯曲区域中。

4. 发明申请

US20100203691A1 High Voltage CMOS Devices 有权
标题翻译：高压CMOS器件
公开(公告)号：US20100203691A1
公开(公告)日：2010-08-12
申请号：US12760182
申请日：2010-04-14
申请人： Chen-Bau Wu , Chien-Shao Tang , Robin Hsieh , Ruey-Hsin Liu , Shun-Liang Hsu
发明人： Chen-Bau Wu , Chien-Shao Tang , Robin Hsieh , Ruey-Hsin Liu , Shun-Liang Hsu
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L27/092 , H01L21/823814 , H01L21/823892 , H01L29/0653 , H01L29/0847 , H01L29/0852 , H01L29/1083 , H01L29/7816 , H01L29/7835
摘要： A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.
摘要翻译：提供了适用于高压应用的晶体管。晶体管形成在具有第一导电类型的深阱的衬底上。形成第一导电类型的第一阱和第二导电类型的第二阱，使得它们不彼此紧邻。第一导电类型和第二导电类型的阱可以同时形成用于低电压装置的各个孔。以这种方式，高压器件可以与具有较少工艺步骤的低电压器件形成在相同的晶片上，从而降低成本和处理时间。可以在与第二阱相对的一侧上邻近第一阱形成掺杂隔离阱以提供进一步的器件隔离。

5. 发明授权

US07719064B2 High voltage CMOS devices 有权
标题翻译：高压CMOS器件
公开(公告)号：US07719064B2
公开(公告)日：2010-05-18
申请号：US12100888
申请日：2008-04-10
申请人： Chen-Bau Wu , Chien-Shao Tang , Robin Hsieh , Ruey-Hsin Liu , Shun-Liang Hsu
发明人： Chen-Bau Wu , Chien-Shao Tang , Robin Hsieh , Ruey-Hsin Liu , Shun-Liang Hsu
IPC分类号： H01L29/78
CPC分类号： H01L27/092 , H01L21/823814 , H01L21/823892 , H01L29/0653 , H01L29/0847 , H01L29/0852 , H01L29/1083 , H01L29/7816 , H01L29/7835
摘要： A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.
摘要翻译：提供了适用于高压应用的晶体管。晶体管形成在具有第一导电类型的深阱的衬底上。形成第一导电类型的第一阱和第二导电类型的第二阱，使得它们不彼此紧邻。第一导电类型和第二导电类型的阱可以同时形成用于低电压装置的各个孔。以这种方式，高压器件可以与具有较少工艺步骤的低电压器件形成在相同的晶片上，从而降低成本和处理时间。可以在与第二阱相对的一侧上邻近第一阱形成掺杂隔离阱以提供进一步的器件隔离。

6. 发明授权

US07547592B2 PMOS depletable drain extension made from NMOS dual depletable drain extensions 有权
标题翻译：由NMOS双可消耗的漏极延伸器制成的PMOS可消耗的漏极延伸
公开(公告)号：US07547592B2
公开(公告)日：2009-06-16
申请号：US11361361
申请日：2006-02-24
申请人： James Douglas Beasom
发明人： James Douglas Beasom
IPC分类号： H01L29/72
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L29/0634 , H01L29/0847 , H01L29/0852 , H01L29/1083 , H01L29/7816 , H01L29/7835
摘要： In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device comprises a source doped to a first conductivity type, a drain extension doped to the first conductivity type separated from the source by a gate, and an extension region doped to a second conductivity type underlying at least a portion of the drain extension adjacent to the gate. The integrated circuit structure also comprises a second complementary MOS device comprising a dual drain extension structure.
摘要翻译：根据本发明的实施例，存在具有包括第一MOS器件的互补集成电路结构的集成电路器件。第一MOS器件包括掺杂到第一导电类型的源极，掺杂到通过栅极与源极分离的第一导电类型的漏极延伸，以及掺杂到第二导电类型的延伸区域，位于漏极延伸部分的至少一部分下方毗邻门。集成电路结构还包括包括双漏极延伸结构的第二互补MOS器件。

7. 发明申请

US20080185629A1 Semiconductor device having variable operating information 审中-公开
标题翻译：具有可变操作信息的半导体器件
公开(公告)号：US20080185629A1
公开(公告)日：2008-08-07
申请号：US11717166
申请日：2007-03-13
申请人： Takashi Nakano , Mitsuhiro Kanayama , Tooru Itabashi , Shigeki Takahashi , Nozomu Akagi
发明人： Takashi Nakano , Mitsuhiro Kanayama , Tooru Itabashi , Shigeki Takahashi , Nozomu Akagi
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/0207 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/0852 , H01L29/7816 , H01L29/7881
摘要： A semiconductor device includes: a semiconductor substrate; multiple MOS type first transistors coupled in parallel with a current path; and a nonvolatile memory for memorizing operating information. Each transistor includes first and second electrodes and a gate electrode for controlling current flowing therebetween. Based on the operating information, each first transistor is selectively set to an active state. When the transistors provide a single transistor, an effective channel width of the single transistor is variable in accordance with the number of the first transistors under the active state.
摘要翻译：半导体器件包括：半导体衬底; 与电流路径并联耦合的多个MOS型第一晶体管; 以及用于存储操作信息的非易失性存储器。每个晶体管包括第一和第二电极以及用于控制电流在其间流动的栅电极。基于操作信息，每个第一晶体管被选择性地设置为活动状态。当晶体管提供单个晶体管时，单个晶体管的有效沟道宽度可以根据在激活状态下的第一晶体管的数量而变化。

8. 发明申请

US20070132033A1 High voltage CMOS devices 有权
标题翻译：高压CMOS器件
公开(公告)号：US20070132033A1
公开(公告)日：2007-06-14
申请号：US11301203
申请日：2005-12-12
申请人： Chen-Bau Wu , Chien-Shao Tang , Robin Hsieh , Ruey-Hsin Liu , Shun-Liang Hsu
发明人： Chen-Bau Wu , Chien-Shao Tang , Robin Hsieh , Ruey-Hsin Liu , Shun-Liang Hsu
IPC分类号： H01L29/76
CPC分类号： H01L27/092 , H01L21/823814 , H01L21/823892 , H01L29/0653 , H01L29/0847 , H01L29/0852 , H01L29/1083 , H01L29/7816 , H01L29/7835
摘要： A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.
摘要翻译：提供了适用于高压应用的晶体管。晶体管形成在具有第一导电类型的深阱的衬底上。形成第一导电类型的第一阱和第二导电类型的第二阱，使得它们不彼此紧邻。第一导电类型和第二导电类型的阱可以同时形成用于低电压装置的各个孔。以这种方式，高压器件可以与具有较少工艺步骤的低电压器件形成在相同的晶片上，从而降低成本和处理时间。可以在与第二阱相对的一侧上邻近第一阱形成掺杂隔离阱以提供进一步的器件隔离。

9. 发明申请

US20070120181A1 Power IGBT with increased robustness 有权
标题翻译：功率IGBT具有增强的鲁棒性
公开(公告)号：US20070120181A1
公开(公告)日：2007-05-31
申请号：US11598243
申请日：2006-11-09
申请人： Holger Ruething , Hans-Joachim Schulze , Manfred Pfaffenlehner
发明人： Holger Ruething , Hans-Joachim Schulze , Manfred Pfaffenlehner
IPC分类号： H01L29/76
CPC分类号： H01L29/7396 , H01L29/0834 , H01L29/0847 , H01L29/0852 , H01L29/32
摘要： A power IGBT includes a semiconductor body having an emitter zone of a first conduction type and a drift zone of a second conduction type proximate to the emitter zone. The IGBT further includes a cell array, each transistor cell of the array having a source zone, a body zone disposed between the source zone and the drift zone, the body zone and source zone short-circuited, and a gate electrode configured to be insulated with respect to the source zone and the body zone. The cell array has a first cell array section with a first cell density and a second cell array section with a second cell density that is lower than the first cell density. The emitter zone has a lower emitter efficiency in a region corresponding to the second cell array section than in a region corresponding to the first cell array section.
摘要翻译：功率IGBT包括具有第一导电类型的发射极区域和接近发射极区域的第二导电类型的漂移区域的半导体本体。 IGBT还包括单元阵列，阵列的每个晶体管单元具有源极区，设置在源极区和漂移区之间的体区，体区和源极区短路，以及被配置为绝缘的栅电极相对于源区和身体区。电池阵列具有具有第一电池密度的第一电池阵列部分和具有低于第一电池密度的第二电池密度的第二电池阵列部分。发射极区在对应于第二单元阵列区的区域中比在与第一单元阵列区对应的区域中的发射极效率更低。

10. 发明授权

US07122876B2 Isolation-region configuration for integrated-circuit transistor 有权
标题翻译：集成电路晶体管的隔离区配置
公开(公告)号：US07122876B2
公开(公告)日：2006-10-17
申请号：US10916133
申请日：2004-08-11
申请人： You-Kuo Wu , Edward Chiang , Shun-Liang Hsu
发明人： You-Kuo Wu , Edward Chiang , Shun-Liang Hsu
IPC分类号： H01L29/00
CPC分类号： H01L29/0852 , H01L21/74 , H01L21/7621 , H01L29/0653 , H01L29/0847 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.
摘要翻译：提供集成电路的晶体管。在第一有源区的阱层中形成第一掺杂阱区。第一掺杂阱区的至少一部分与晶体管的栅电极相邻。在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。第二隔离部分的至少一部分比第一隔离部分低。漏极掺杂区形成在第一掺杂阱区的凹槽中。第二隔离部分位于栅电极和漏极掺杂区之间。

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