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1. 发明申请

US20190157401A1 Method of Manufacturing a Power Semiconductor Device 审中-公开
公开(公告)号：US20190157401A1
公开(公告)日：2019-05-23
申请号：US16235726
申请日：2018-12-28
申请人： Infineon Technologies AG
发明人： Matthias Kuenle , Daniel Schloegl , Hans-Joachim Schulze , Christoph Weiss
IPC分类号： H01L29/36 , H01L29/861 , H01L29/66 , H01L21/265 , H01L29/08 , H01L29/10 , H01L29/739 , H01L29/78
CPC分类号： H01L29/36 , H01L21/265 , H01L29/0804 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/6609 , H01L29/66136 , H01L29/66325 , H01L29/66333 , H01L29/66674 , H01L29/66712 , H01L29/7393 , H01L29/7395 , H01L29/7801 , H01L29/7802 , H01L29/861
摘要： A method of manufacturing a power semiconductor device includes: creating a doped contact region on top of a surface of a carrier; creating, on top of the contact region, a doped transition region having a maximum dopant concentration of at least 0.5*1015 cm−3 for at least 70% of a total extension of the doped transition region in an extension direction and a maximal dopant concentration gradient of at most 3*1022 cm−4, wherein a lower subregion of the doped transition region is in contact with the contact region and has a maximum dopant concentration at least 100 times higher than a maximum dopant concentration of an upper subregion of the doped transition region; and creating a doped drift region on top of the upper subregion of the doped transition region, the doped drift region having a lower dopant concentration than the upper subregion of the doped transition region.

2. 发明申请

US20180212041A1 DEVICES AND METHODS FOR A POWER TRANSISTOR HAVING A SCHOTTKY OR SCHOTTKY-LIKE CONTACT 审中-公开
公开(公告)号：US20180212041A1
公开(公告)日：2018-07-26
申请号：US15927693
申请日：2018-03-21
申请人： Silicet, LLC
发明人： Gary M. DOLNY , William R. RICHARDS, JR. , Randall MILANOWSKI
IPC分类号： H01L29/66 , H01L29/872 , H01L29/49 , H01L21/78 , H01L29/78 , H01L29/10 , H01L29/08 , H01L29/423 , H01L21/28 , H01L21/225 , H01L21/8238 , H01L21/8234 , H01L27/088 , H01L27/095
CPC分类号： H01L29/66643 , H01L21/225 , H01L21/28061 , H01L21/28123 , H01L21/7813 , H01L21/823412 , H01L21/823418 , H01L21/823814 , H01L21/823835 , H01L27/088 , H01L27/095 , H01L29/0856 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/42372 , H01L29/47 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/66674 , H01L29/66689 , H01L29/7806 , H01L29/7813 , H01L29/7816 , H01L29/7825 , H01L29/7835 , H01L29/7839 , H01L29/872
摘要： Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.

3. 发明授权

US09559187B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09559187B2
公开(公告)日：2017-01-31
申请号：US14842513
申请日：2015-09-01
申请人： SK hynix Inc.
发明人： Kwang-Sik Ko , Kuem-Ju Lee , Joo-Won Park
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/423 , H01L29/08 , H01L21/8234 , H01L29/06 , H01L21/265 , H01L29/10
CPC分类号： H01L29/66659 , H01L21/26513 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L29/0615 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/0873 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66492 , H01L29/6659 , H01L29/66674 , H01L29/66681 , H01L29/7816 , H01L29/7833 , H01L29/7835
摘要： A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an Nth epitaxial layer and an (N+1)th epitaxial layer among the multiple epitaxial layers, where N is a natural number, a body region formed in an uppermost epitaxial layer among the multiple epitaxial layers and a deep well formed in the uppermost epitaxial layer to surround the body region and to be coupled with the second buried impurity regions that share the uppermost epitaxial layer.
摘要翻译：半导体器件包括堆叠在支撑衬底上的多个外延层，形成为在多个外延层中共享具有最低外延层的支撑衬底的第一掩埋杂质区，形成为与多个外延层耦合的第二埋入杂质区第一掩埋杂质区，并且在多个外延层中共享第N外延层和第（N + 1）外延层，其中N是自然数，形成在多个外延层中的最外延层中的体区和深良好地形成在最上层的外延层中以围绕体区，并与共享最上层的外延层的第二掩埋杂质区耦合。

4. 发明申请

US20160307849A1 Semiconductor Device and Manufacturing Method 审中-公开
标题翻译：半导体器件及制造方法
公开(公告)号：US20160307849A1
公开(公告)日：2016-10-20
申请号：US15095650
申请日：2016-04-11
申请人： Infineon Technologies AG
发明人： Thorsten Meyer , Stephan Senn
IPC分类号： H01L23/532 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L29/40
CPC分类号： H01L23/53271 , H01L27/0922 , H01L29/407 , H01L29/66674 , H01L29/66734 , H01L29/78 , H01L29/7801 , H01L29/7811 , H01L29/7813
摘要： The present disclosure relates to a semiconductor device, comprising a semiconductor substrate; a trench extending into the semiconductor substrate, wherein the trench is partly filled with an electrically conductive structure insulated from the semiconductor substrate; a polysilicon or amorphous silicon routing structure laterally bridging the trench; and an insulation layer between the trench and the routing structure.
摘要翻译：本公开涉及一种半导体器件，包括半导体衬底; 延伸到所述半导体衬底中的沟槽，其中所述沟槽部分地填充有与所述半导体衬底绝缘的导电结构; 横向桥接沟槽的多晶硅或非晶硅布线结构; 以及沟槽和布线结构之间的绝缘层。

5. 发明授权

US09443971B2 Semiconductor to metal transition 有权
标题翻译：半导体到金属过渡
公开(公告)号：US09443971B2
公开(公告)日：2016-09-13
申请号：US14940797
申请日：2015-11-13
申请人： Infineon Technologies AG
发明人： Andreas Haertl , Frank Hille , Francisco Javier Santos Rodriguez , Daniel Schloegl , Andre Rainer Stegner , Christoph Weiss
IPC分类号： H01L29/00 , H01L21/22 , H01L21/38 , H01L29/78 , H01L29/739 , H01L29/66 , H01L29/10 , H01L29/06
CPC分类号： H01L29/063 , H01L21/26506 , H01L21/28568 , H01L29/0607 , H01L29/1095 , H01L29/167 , H01L29/32 , H01L29/36 , H01L29/417 , H01L29/45 , H01L29/66136 , H01L29/66325 , H01L29/66333 , H01L29/66674 , H01L29/7393 , H01L29/7395 , H01L29/7801 , H01L29/861
摘要： A semiconductor device includes a diffusion barrier layer, a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region in contact with the diffusion barrier layer, the contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing the lifetime and/or the mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region.
摘要翻译：半导体器件包括扩散阻挡层，具有第一导电类型的第一电荷载流子的第一半导体区域和具有第二电荷载流子的第二半导体区域。第一半导体区域包括与第二半导体区域接触的过渡区域，过渡区域具有第一电荷载流子的第一浓度，与扩散阻挡层接触的接触区域，接触区域具有第一浓度的第一电荷载体，其中第二浓度高于第一浓度，以及在接触区域和过渡区域之间的损伤区域。损伤区域被配置为与接触区域和过渡区域的第一电荷载流子的寿命和/或迁移率相比，减小损伤区域的第一电荷载流子的寿命和/或迁移率。

6. 发明授权

US09312385B2 Semiconductor device and manufacturing method of semiconductor device 有权
标题翻译：半导体器件及半导体器件的制造方法
公开(公告)号：US09312385B2
公开(公告)日：2016-04-12
申请号：US14239249
申请日：2012-06-07
申请人： Daisuke Matsumoto , Naoki Tega , Yasuhiro Shimamoto
发明人： Daisuke Matsumoto , Naoki Tega , Yasuhiro Shimamoto
IPC分类号： H01L27/12 , H01L21/336 , H01L29/78 , H01L29/66 , H01L29/06 , H01L29/10 , H01L27/088 , H01L29/16
CPC分类号： H01L29/7838 , H01L27/0883 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/66674 , H01L29/66712 , H01L29/7801 , H01L29/7802
摘要： A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106); a p body layer (103) which surrounds the source layer and has a channel region; an n−-type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p+ layer (109) which is disposed in the p body layer (103), extends to a portion below the n+ source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p+ layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.
摘要翻译：提供了一种用于改善半导体器件（DMOSFET）的特性的技术。半导体器件被配置为包括：设置在SiC衬底（106）的第一表面侧的上部的n型源极层（102）; 围绕源层并具有沟道区的p体层（103）; 与p体层（103）接触的n型漂移层（107）; 栅极电极，其经由栅极绝缘膜设置在所述沟道区域的上部; 并且设置在p体层（103）中的第一p +层（109）延伸到n +源极层（102）下方的部分，并且用作具有高于p的杂质浓度的掩埋半导体区域身体层（103）。以这种方式，由于第一p +层（109）形成在p体层（103）的中间，所以可以降低p体层（103）的扩散阻力。因此，可以使寄生双极晶体管更难以导通。

7. 发明授权

US09306034B2 Method and apparatus for power device with multiple doped regions 有权
标题翻译：具有多个掺杂区域的功率器件的方法和装置
公开(公告)号：US09306034B2
公开(公告)日：2016-04-05
申请号：US14187950
申请日：2014-02-24
申请人： Vanguard International Semiconductor Corporation
发明人： Shang-Hui Tu , Chih-Jen Huang , Jui-Chun Chang , Shin-Cheng Lin , Yu-Hao Ho , Wen-Hsin Lin
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10 , H01L21/70
CPC分类号： H01L29/7801 , H01L21/2652 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1045 , H01L29/105 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66674 , H01L29/66681 , H01L29/66712 , H01L29/7802 , H01L29/7816 , H01L29/7823 , H01L29/7835
摘要： A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
摘要翻译：提供半导体器件。该器件包括具有第一导电类型的衬底。该器件还包括漏极区域，源极区域和设置在衬底中的阱区域。阱区域设置在漏极区域和源极区域之间并且具有与第一导电类型相反的第二导电类型。该器件还包括设置在阱区内的多个掺杂区域。掺杂区域彼此垂直和水平地偏移。每个掺杂区域包括具有第一导电类型的下部分和堆叠在下部区域上并具有第二导电类型的上部。

8. 发明授权

US09252251B2 Semiconductor component with a space saving edge structure 有权
标题翻译：半导体元件具有节省空间的边缘结构
公开(公告)号：US09252251B2
公开(公告)日：2016-02-02
申请号：US13330205
申请日：2011-12-19
申请人： Franz Hirler , Ralf Siemieniec , Christian Geissler , Oliver Blank , Maximilian Roesch
发明人： Franz Hirler , Ralf Siemieniec , Christian Geissler , Oliver Blank , Maximilian Roesch
IPC分类号： H01L29/739 , H01L29/66 , H01L29/78 , H01L29/861 , H01L29/872 , H01L29/06 , H01L29/40 , H01L29/423
CPC分类号： H01L29/7397 , H01L29/0615 , H01L29/0623 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1045 , H01L29/105 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/42376 , H01L29/66674 , H01L29/66734 , H01L29/7801 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.
摘要翻译：公开了半导体部件。一个实施例包括半导体本体，其包括具有至少一个有源分量区的第一半导体层，具有多个沟槽的单元阵列和至少一个单元阵列边缘区。单元阵列边缘区域仅布置在单元阵列的边缘区域中，邻接单元阵列的至少一个沟槽，并且至少部分地布置在单元阵列中的至少一个沟槽的下方。

9. 发明申请

US20150349092A1 TRENCH GATE TRENCH FIELD PLATE SEMI-VERTICAL SEMI-LATERAL MOSFET 审中-公开
公开(公告)号：US20150349092A1
公开(公告)日：2015-12-03
申请号：US14821085
申请日：2015-08-07
申请人： Texas Instruments Incorporated
发明人： Marie DENISON , Sameer PENDHARKAR , Guru MATHUR
IPC分类号： H01L29/66 , H01L29/10 , H01L29/06 , H01L29/417 , H01L21/324 , H01L21/225 , H01L29/78 , H01L29/08 , H01L21/265
CPC分类号： H01L29/66712 , H01L21/225 , H01L21/26513 , H01L21/324 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/42368 , H01L29/66674 , H01L29/66734 , H01L29/7801 , H01L29/7809 , H01L29/7813
摘要： A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.

10. 发明授权

US09153687B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09153687B2
公开(公告)日：2015-10-06
申请号：US14135011
申请日：2013-12-19
申请人： SK hynix Inc.
发明人： Kwang-Sik Ko , Kuem-Ju Lee , Joo-Won Park
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L29/08 , H01L21/8234 , H01L29/06
CPC分类号： H01L29/66659 , H01L21/26513 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L29/0615 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/0873 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66492 , H01L29/6659 , H01L29/66674 , H01L29/66681 , H01L29/7816 , H01L29/7833 , H01L29/7835
摘要： A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an Nth epitaxial layer and an (N+1)th epitaxial layer among the multiple epitaxial layers, where N is a natural number, a body region formed in an uppermost epitaxial layer among the multiple epitaxial layers and a deep well formed in the uppermost epitaxial layer to surround the body region and to be coupled with the second buried impurity regions that share the uppermost epitaxial layer.
摘要翻译：半导体器件包括堆叠在支撑衬底上的多个外延层，形成为在多个外延层中共享具有最低外延层的支撑衬底的第一掩埋杂质区，形成为与多个外延层耦合的第二埋入杂质区第一掩埋杂质区，并且在多个外延层中共享第N外延层和第（N + 1）外延层，其中N是自然数，形成在多个外延层中的最外延层中的体区和深良好地形成在最上层的外延层中以围绕体区，并与共享最上层的外延层的第二掩埋杂质区耦合。

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