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1. 发明申请

US20180309413A1 CORRECTING FOR NON-LINEARITY IN AN AMPLIFIER PROVIDING A DIFFERENTIAL OUTPUT 审中-公开
公开(公告)号：US20180309413A1
公开(公告)日：2018-10-25
申请号：US15957927
申请日：2018-04-20
申请人： Aura Semiconductor Pvt. Ltd
发明人： Arnold J. D'Souza , Shyam Somayajula
IPC分类号： H03F1/32 , H03F3/45 , H03F3/21 , H03F1/02 , H03M1/38
CPC分类号： H03F1/32 , H03F1/02 , H03F1/0227 , H03F1/3211 , H03F3/21 , H03F3/45475 , H03F3/45937 , H03F2200/129 , H03F2200/331 , H03F2201/3215 , H03F2203/45522 , H03F2203/45528 , H03F2203/45594 , H03M1/38
摘要： A fully differential amplifier includes a first feedback resistance, a second feedback resistance, a first input resistance and a second input resistance. A first ratio of the first feedback resistance to the first input resistance is equalized with that of a reference ratio of a pair of reference resistances. Similarly a second ratio of the second feedback resistance to the second input resistance is also equalized with that of the reference ratio. Such equalization operations may be performed during a calibration phase prior to normal operation of the fully differential amplifier. Accordingly, when a common mode voltage present on each of the first output terminal and the second output terminal varies during normal operation, contribution of an erroneous differential signal component across the pair of differential output terminals is prevented.

2. 发明申请

US20170149388A1 DIFFERENTIAL SUMMING NODE 审中-公开
公开(公告)号：US20170149388A1
公开(公告)日：2017-05-25
申请号：US15342009
申请日：2016-11-02
申请人： NXP B.V.
发明人： Shagun Bajoria , Muhammed Bolatkale , Robert Rutten , Lucien Breems , Johannes Brekelmans , Jan Niehof
IPC分类号： H03D7/12 , H03M3/00
CPC分类号： H03D7/12 , H03F1/3211 , H03F3/45183 , H03F3/45475 , H03F2200/331 , H03F2203/45138 , H03M3/422 , H03M3/454 , H03M3/476
摘要： A summing node is provided for summing a first and second differential signals. Each of the first and second differential signals comprise respective direct and inverse signal components. The summing node comprises a first differential transistor pair comprising a first and second input and coupled to a first and second output. The summing node further comprises a second differential transistor pair comprising a third and fourth input and coupled to the first and second output. The first and fourth inputs are respectively coupled to the direct and inverse signal components of the first differential signal and the second and third inputs are respectively coupled to the direct and inverse signal components of the second differential signal.

3. 发明申请

US20160309274A1 IMPLEMENTATION METHOD AND DEVICE OF MULTI-BIT MODULATION-BASED DIGITAL SPEAKER SYSTEM 有权
标题翻译：基于多点调制的数字扬声器系统的实现方法和设备
公开(公告)号：US20160309274A1
公开(公告)日：2016-10-20
申请号：US15101147
申请日：2014-12-02
申请人： SUZHOU SONAVOX ELECTRONICS CO., LTD.
发明人： DENGYONG MA , JUN YANG , JIANMING ZHOU , GUOQIANG CHAI , YEFENG CAI , YONGSHENG MU
IPC分类号： H04S5/00 , H04R5/04 , H03F3/183 , H03M3/00 , H03F3/21 , H04R5/02 , H04R3/04
CPC分类号： H04S5/00 , G06F3/16 , H03F3/183 , H03F3/185 , H03F3/21 , H03F3/217 , H03F3/2175 , H03F3/68 , H03F2200/03 , H03F2200/331 , H03M3/04 , H03M3/338 , H03M3/424 , H03M3/508 , H04R1/005 , H04R3/04 , H04R5/02 , H04R5/04 , H04R2201/403
摘要： The present invention discloses an implementation method and a device of a multi-bit Δ-Σ modulation-based digital speaker system. The method comprises, 1) digital format converting; 2) oversampling interpolation filtering; 3) multi-bit Δ-Σ modulating; 4) thermometer coding; 5) multi-channel mismatch shaping; 6) coding format converting; 7) multi-channel digital power-amplifying; 8) driving a speaker array or a multiple voice coil speaker to sound. The device comprises: a digital input interface, an oversampling interpolation filter, a multi-bit Δ-Σ modulator, a thermometer coder, a multi-channel mismatch shaper, a coding format converter, a multi-channel digital power-amplifier, and a speaker array or a multiple voice coil speaker; each portion being connected in proper order. The present invention can achieve a high-power output under a low-voltage power supply, save power consumption, implement a single-chip integration of a multi-channel reproducing system, reduce the volume and weight of the system and the implementing cost, and improve the quality of the reproduced sound.
摘要翻译：本发明公开了一种基于多位Δ-Σ调制的数字扬声器系统的实现方法和装置。该方法包括：1）数字格式转换; 2）过采样内插滤波; 3）多位Δ-Σ调制; 4）温度计编码; 5）多通道失配成形; 6）编码格式转换; 7）多通道数字功率放大; 8）驱动扬声器阵列或多个音圈扬声器发出声音。该装置包括：数字输入接口，过采样内插滤波器，多位Δ-Σ调制器，温度计编码器，多通道失配整形器，编码格式转换器，多通道数字功率放大器和扬声器阵列或多个音圈扬声器; 每个部分按正确的顺序连接。本发明可以在低电压电源下实现大功率输出，节省功耗，实现多通道再现系统的单芯片集成，降低系统的体积和重量以及实施成本，提高再现声音的质量。

4. 发明申请

US20160248470A1 TRANSMITTER/RECEIVER APPARATUS, TRANSMITTER APPARATUS AND TRANSMITTING/RECEIVING METHOD 有权
标题翻译：发射机/接收机装置，发射机装置和发射/接收方法
公开(公告)号：US20160248470A1
公开(公告)日：2016-08-25
申请号：US15027767
申请日：2014-10-15
申请人： NEC CORPORATION
发明人： Kazuaki KUNIHIRO , Shinichi HORI
IPC分类号： H04B1/44 , H03F3/24 , H04B1/3827 , H04L27/36 , H03F3/195 , H04L27/38 , H03F3/217 , H03F3/213
CPC分类号： H04B1/44 , H03F3/195 , H03F3/213 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/245 , H03F2200/171 , H03F2200/294 , H03F2200/331 , H03F2200/451 , H04B1/3833 , H04L27/36 , H04L27/38
摘要： A transmitter/receiver apparatus including: a transmitter/receiver terminal; a switching amplifier that includes a low-side switching element connected between a ground terminal and a pulse output terminal and a high-side switching element connected between the pulse output terminal and a power supply terminal and that outputs a pulse signal from the pulse output terminal; a filter that passes therethrough and outputs as a transmitted signal a predetermined frequency component of the pulse signal from a transmitter terminal; and a transmit/receive switch unit that switches the connection status between the transmitter/receiver terminal and the transmitter terminal and also switches the connection status between the transmitter/receiver terminal and a receiver terminal. During receiving, on the basis of the connection status between the transmitter/receiver terminal and the transmitter terminal, the low-side and high-side switching elements are fixed to conductive and non-conductive states, respectively, to non-conductive and conductive states, respectively, or both to non-conductive states.
摘要翻译：一种发射机/接收机装置，包括：发射机/接收机终端; 开关放大器，包括连接在接地端子和脉冲输出端子之间的低侧开关元件和连接在脉冲输出端子和电源端子之间的高侧开关元件，并且从脉冲输出端子输出脉冲信号 ; 滤波器，其通过其并作为发送信号从发射机终端输出脉冲信号的预定频率分量; 以及发送/接收终端与发送终端之间的连接状态切换的发送接收开关单元，也切换发送接收端与接收端之间的连接状态。在接收期间，基于发射机/接收机终端与发射机终端之间的连接状态，低侧和高侧开关元件分别被固定为导电和非导通状态，以非导通和导通状态，或两者分别为非导通状态。

5. 发明申请

US20160204793A1 SIGMA-DELTA ADC WITH DITHER 有权
标题翻译： SIGMA-DELTA ADC与DITHER
公开(公告)号：US20160204793A1
公开(公告)日：2016-07-14
申请号：US14842353
申请日：2015-09-01
申请人： MediaTek Inc.
发明人： Frank Op 't Eynde , Chi-Lun Lo , Michael A. Ashburn
IPC分类号： H03M3/00
CPC分类号： H03M3/332 , H03F3/505 , H03F2200/331 , H03F2203/5021 , H03F2203/5031 , H03F2203/5033 , H03M1/00 , H03M1/0641 , H03M1/12 , H03M3/458
摘要： Systems and methods for reducing spurious noise tones in sigma-delta analog-to-digital converters (ADCs) are described. A dither signal may be added to two differential input signals of a pseudo-differential sigma-delta ADC. The dither signal may be generated by a pseudo-random bit sequence generator and applied to two input buffers, which add the dither signal to received differential analog input signals. The dithered signals may be digitized by two independent sigma-delta ADCs and then subtracted to remove the dither signal from an overall digital output signal.
摘要翻译：描述了用于减小Σ-Δ模数转换器（ADC）中的杂散噪声音调的系统和方法。可以将抖动信号添加到伪差分Σ-ΔADC的两个差分输入信号。抖动信号可以由伪随机比特序列发生器产生，并被施加到两个输入缓冲器，其将抖动信号加到接收到的差分模拟输入信号。抖动信号可以由两个独立的Σ-ΔADC数字化，然后被减去以从整体数字输出信号中去除抖动信号。

6. 发明授权

US09385745B1 Sigma-delta ADC with dither 有权
标题翻译：带抖动的Σ-ΔADC
公开(公告)号：US09385745B1
公开(公告)日：2016-07-05
申请号：US14842353
申请日：2015-09-01
申请人： MediaTek Inc.
发明人： Frank Op 't Eynde , Chi-Lun Lo , Michael A. Ashburn
IPC分类号： H03M1/20 , H03M3/00 , H03M1/00 , H03M1/12 , H03M1/06
CPC分类号： H03M3/332 , H03F3/505 , H03F2200/331 , H03F2203/5021 , H03F2203/5031 , H03F2203/5033 , H03M1/00 , H03M1/0641 , H03M1/12 , H03M3/458
摘要： Systems and methods for reducing spurious noise tones in sigma-delta analog-to-digital converters (ADCs) are described. A dither signal may be added to two differential input signals of a pseudo-differential sigma-delta ADC. The dither signal may be generated by a pseudo-random bit sequence generator and applied to two input buffers, which add the dither signal to received differential analog input signals. The dithered signals may be digitized by two independent sigma-delta ADCs and then subtracted to remove the dither signal from an overall digital output signal.
摘要翻译：描述了用于减小Σ-Δ模数转换器（ADC）中的杂散噪声音调的系统和方法。可以将抖动信号添加到伪差分Σ-ΔADC的两个差分输入信号。抖动信号可以由伪随机比特序列发生器产生，并被施加到两个输入缓冲器，其将抖动信号加到接收到的差分模拟输入信号。抖动信号可以由两个独立的Σ-ΔADC数字化，然后被减去以从整体数字输出信号中去除抖动信号。

7. 发明申请

US20160191294A1 TRANSMITTER AND METHOD OF TRANSMITTING 审中-公开
公开(公告)号：US20160191294A1
公开(公告)日：2016-06-30
申请号：US15063146
申请日：2016-03-07
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Rahmi Hezar , Lei Ding , Baher Haroun
IPC分类号： H04L27/34 , H04B1/02
CPC分类号： H04L27/3411 , H03F1/02 , H03F1/0294 , H03F3/19 , H03F3/2175 , H03F3/245 , H03F2200/331 , H03F2200/336 , H03F2200/451 , H04B1/02 , H04B14/062 , H04L27/2053
摘要： At least one tone is generated. An output signal is generated in response to an input signal and the at least one tone. The output signal is modulated. The input signal and the at least one tone are represented in the modulated output signal. The at least one tone is outside a bandwidth of the input signal as represented in the modulated output signal. The modulated output signal is amplified. The at least one tone in the amplified signal is attenuated after the amplifying.

8. 发明申请

US20160127162A1 TRANSMISSION CIRCUIT 有权
标题翻译：传输电路
公开(公告)号：US20160127162A1
公开(公告)日：2016-05-05
申请号：US14894127
申请日：2014-05-19
申请人： NEC CORPORATION
发明人： Yoshiaki DOI
IPC分类号： H04L27/20
CPC分类号： H04L27/2092 , H03F3/2175 , H03F2200/331 , H04L27/361
摘要： The transmission circuit includes a comparator that converts a phase-modulated signal from an orthogonal modulator into a pulse signal so as to use the pulse signal as the sampling clock of the a delta-sigma modulator, and an asynchronous clock transfer unit and an interpolating circuit, disposed between a circuit operating based on the baseband clock and the delta-sigma modulator. The asynchronous clock transfer unit converts the amplitude component signal synchronized with the baseband clock, into an amplitude component signal synchronized with an N-frequency divided clock obtained by dividing the frequency of the sampling clock by N. The interpolating circuit interpolates the output signal from the asynchronous clock transfer unit so that the amount of change of one sample in the N-frequency divided clock becomes equal to the amount of change of one sample in the sampling clock.
摘要翻译：发送电路包括将来自正交调制器的相位调制信号转换为脉冲信号的比较器，以便将脉冲信号用作Δ-Σ调制器的采样时钟，以及异步时钟传送单元和内插电路，设置在基于基带时钟和delta-sigma调制器工作的电路之间。异步时钟传送单元将与基带时钟同步的幅度分量信号转换成与通过将采样时钟的频率除以N而获得的N分频时钟同步的振幅分量信号。内插电路内插来自异步时钟传送单元，使得N分频时钟中的一个采样的变化量等于采样时钟中的一个采样的变化量。

9. 发明授权

US09204215B2 One-bit digital-to-analog converter offset cancellation 有权
标题翻译：一位数模转换器偏移消除
公开(公告)号：US09204215B2
公开(公告)日：2015-12-01
申请号：US14136484
申请日：2013-12-20
申请人： ST-Ericsson SA
发明人： Christian Fraisse , Angelo Nagari
IPC分类号： H04B15/00 , H04R3/00 , H03F3/217 , H03F3/45 , H03M3/00
CPC分类号： H04R3/00 , H03F3/2175 , H03F3/45968 , H03F2200/331 , H03F2200/375 , H03M3/384 , H03M3/50
摘要： There is described Audio driver circuit comprising a main, 1-bit digital-to-analog converter, adapted to receive a 1-bit oversampled digital audio signal. Thanks to an auxiliary digital-to-analog converter which converts into the analog domain a digital offset compensation value stored in e.g. an OTP memory register 34, and to a summing and filtering arrangement, it is possible to reduce the offset cancellation granularity in order to compensate for the offset of the main digital-to-analog converter in the output signal.
摘要翻译：描述了音频驱动器电路，其包括适用于接收1位过采样数字音频信号的主1位数模转换器。由于辅助数模转换器，其转换成模拟域，数字偏移补偿值存储在例如数据位。 OTP存储器寄存器34，并且对于求和和滤波装置，可以减小偏移消除粒度，以便补偿主数模转换器在输出信号中的偏移。

10. 发明申请

US20140285269A1 High Efficiency Amplification 审中-公开
标题翻译：高效扩增
公开(公告)号：US20140285269A1
公开(公告)日：2014-09-25
申请号：US14299184
申请日：2014-06-09
申请人： Martin Paul Wilson
发明人： Martin Paul Wilson
IPC分类号： H03F1/02 , H03F3/19 , H03F3/21
CPC分类号： H03F1/0222 , H03F1/00 , H03F1/02 , H03F1/025 , H03F3/189 , H03F3/19 , H03F3/21 , H03F3/245 , H03F2200/102 , H03F2200/331 , H03F2200/451 , H03F2200/504 , H03F2200/511
摘要： A radio frequency amplification stage comprising: an amplifier for receiving an input signal to be amplified and a power supply voltage; and a power supply voltage stage for supplying said power supply voltage, comprising: means for providing a reference signal representing the envelope of the input signal; means for selecting one of a plurality of supply voltage levels in dependence on the reference signal; and means for generating an adjusted selected power supply voltage, comprising an ac amplifier for amplifying a difference between the reference signal and one of the selected supply voltage level or the adjusted selected supply voltage level, and a summer for summing the amplified difference with the selected supply voltage to thereby generate the adjusted supply voltage.
摘要翻译：一种射频放大级，包括：放大器，用于接收待放大的输入信号和电源电压; 以及用于提供所述电源电压的电源电压级，包括：用于提供表示所述输入信号的包络的参考信号的装置; 用于根据参考信号选择多个电源电压电平中的一个的装置; 以及用于产生经调整的所选择的电源电压的装置，包括用于放大参考信号与所选择的电源电压电平或所调整的所选电源电压电平之一之间的差的交流放大器，以及用于将放大的差与所选择的电源电压相加的加法器供给电压，从而生成调整后的电源电压。

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