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1. 发明授权

US10634563B2 Phase measurement device and instrument in which phase measurement device is applied 有权
公开(公告)号：US10634563B2
公开(公告)日：2020-04-28
申请号：US16098958
申请日：2017-04-27
申请人： NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
发明人： Wataru Kokuyama
IPC分类号： G01J9/02 , G01R29/26 , G01R25/00 , H03D13/00 , G01B11/14 , G01R25/08 , H03L7/091
CPC分类号： G01J9/02 , G01B11/14 , G01R25/00 , G01R25/08 , G01R29/26 , H03D13/00 , H03L7/091
摘要： A count processor counts a zero crossing detection count C. A fraction processor for calculating a fraction Fj (j=1 to L) of the zero crossing detection count on the basis of the digital signal at sampling timings immediately before a zero crossing specifying and when the zero crossing specifying, and computing a fraction processing parameter Gj=Nj−Fj using a zero crossing detection number Nj(0≤Nj≤N−1) in a period corresponding to a sampling count N necessary for averaging determined in advance. The averaging is performed according to the following formula, where C is the output of the count processor at the end of an averaging period and Gj (j=1 to L) is L fraction processing parameters (L indicates the number of Gj included between the averaging counts N) computed by the fraction processor, and the phase of the digital signal is computed, whereby the phase is calculated on the basis of an input signal digital value obtained by an AD converter.

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2. 发明申请

US20170126236A1 Reference-less Frequency Detector With High Jitter Tolerance 审中-公开
公开(公告)号：US20170126236A1
公开(公告)日：2017-05-04
申请号：US15394364
申请日：2016-12-29
申请人： Futurewei Technologies, Inc.
发明人： Liang Gu , Yuming Cao , Gong Lei , Yen Dang , Yifan Gu , Hungyi Lee , Mamatha Deshpande , Shou-Po Shih , Yan Duan
IPC分类号： H03L7/099 , H03L7/08 , H03K5/135 , H03K5/14 , H03K19/20 , H03K19/0948
CPC分类号： H03L7/099 , H03D13/00 , H03K5/135 , H03K5/14 , H03K19/0948 , H03K19/20 , H03K2005/00078 , H03L7/0807 , H03L7/085 , H03L7/089 , H04L7/0008 , H04L7/0016 , H04L7/033
摘要： An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.

3. 发明申请

US20160349297A1 METHOD FOR USING AN ACCURATE ADJUSTABLE HIGH-FREQUENCY PHASE-DETECTOR 有权
标题翻译：使用精确可调高频相位检测器的方法
公开(公告)号：US20160349297A1
公开(公告)日：2016-12-01
申请号：US15111569
申请日：2015-05-18
申请人： CATENA HOLDING B.V.
发明人： Peter van der Cammen
IPC分类号： G01R25/00 , H03K5/26 , H03D7/14
CPC分类号： G01R25/00 , G01R25/02 , G01R25/04 , H03D7/14 , H03D7/1433 , H03D7/1458 , H03D13/00 , H03K5/26
摘要： The method determines an input phase differential (Δφ) between two input signals. A phase detector is provided that has pairs of transistors and a first impedance (R1) connected to a first branch carrying a first signal (Iout_left) and a second impedance (R2) connected to a second branch carrying a second signal (Iout_right). The first signal (Iout_left) in the first branch is set as a first sum of a common mode output signal (Icm) and a differential mode output signal (Idm). The second signal (Iout_right) in the second branch is set as a second sum of the common mode output signal (Icm) minus the differential mode output signal (Idm). A relationship between the first impedance (R1) and the second impedance (R2) is adjusted until a differential mode output voltage (Vdm) of the phase detector is zero. The input phase differential (Δφ) is determined when the differential mode output voltage (Vdm) is zero.
摘要翻译：该方法确定两个输入信号之间的输入相位差（Δφ）。提供一种相位检测器，其具有成对的晶体管和连接到承载第一信号（Iout_left）的第一分支和连接到承载第二信号（Iout_right）的第二分支的第二阻抗（R2））的第一阻抗（R1）。第一分支中的第一信号（Iout_left）被设置为共模输出信号（Icm）和差模输出信号（Idm）的第一和。第二分支中的第二信号（Iout_right）被设置为共模输出信号（Icm）减去差模输出信号（Idm）的第二和。调整第一阻抗（R1）和第二阻抗（R2）之间的关系，直到相位检测器的差模输出电压（Vdm）为零为止。当差模输出电压（Vdm）为零时，确定输入相位差（Δφ）。

4. 发明申请

US20160266185A1 System and Method for a Phase Detector 审中-公开
公开(公告)号：US20160266185A1
公开(公告)日：2016-09-15
申请号：US15074429
申请日：2016-03-18
申请人： Infineon Technologies AG
发明人： Valentyn Solomko
IPC分类号： G01R25/00 , H04B1/40 , H03F3/19
CPC分类号： G01R25/005 , G01R25/00 , H03D13/00 , H03F3/19 , H03F2200/423 , H03F2200/451 , H04B1/40
摘要： In accordance with an embodiment, a method of detecting a phase difference between a first signal and a second signal include latching a state of the first signal using the second signal as a clock to produce a first latched signal, latching a state of the second signal using the first signal as a clock to produce a second latched signal summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.

5. 发明授权

US09137066B2 Method and apparatus for generating a metric for use in one or more of lock detection, SNR estimation, and modulation classification 有权
标题翻译：用于生成用于锁定检测，SNR估计和调制分类中的一个或多个的度量的方法和装置
公开(公告)号：US09137066B2
公开(公告)日：2015-09-15
申请号：US13882780
申请日：2011-11-01
申请人： Yair Linn
发明人： Yair Linn
IPC分类号： H04L27/00 , H04L27/20 , H04L27/38 , H03J7/06 , H03D13/00 , H04B17/00 , H04B17/391
CPC分类号： H04L27/20 , H03D13/00 , H03J7/065 , H04B17/336 , H04B17/391 , H04L27/3818
摘要： The present disclosure is directed at a method and apparatus for generating a metric for use in any one or more of lock detection, SNR estimation, and modulation classification. To generate the metric, an input angle in the form of a symbol phase or a difference in symbol phases is used to evaluate a base function. The base function relates possible metrics to possible input angles using a triangle wave having its maxima or minima at ideal input angles, and the other of its maxima or minima at angles midway the ideal input angles. Described are embodiments that are one or more of non-data aided; that may be implemented relatively efficiently in hardware; that can function using one sample/symbol; that can achieve relatively good detection certainty using relatively few estimates; and that can be used to implement modulation classifiers, lock detectors, and SNR estimators that are resilient to imperfections in automatic gain control.
摘要翻译：本公开涉及用于生成用于锁定检测，SNR估计和调制分类中的任一个或多个的度量的方法和装置。为了产生度量，使用符号相位形式的输入角或符号相位的差异来评估基本函数。基本功能将可能的度量与使用其理想输入角度的最大值或最小值的三角波以及在理想输入角度的中间角度处的最大值或最小值中的另一个相关联的可能的输入角度。描述了作为非数据辅助的一个或多个的实施例; 这可以在硬件中相对有效地实现; 可以使用一个样本/符号来运行; 使用相对较少的估计可以获得相对较好的检测确定性; 并且可以用于实现对自动增益控制中的缺陷有弹性的调制分类器，锁定检测器和SNR估计器。

6. 发明授权

US08847641B2 Phase comparison device and DLL circuit 有权
标题翻译：相位比较器和DLL电路
公开(公告)号：US08847641B2
公开(公告)日：2014-09-30
申请号：US14232371
申请日：2012-07-17
申请人： Shoichiro Kashiwakura
发明人： Shoichiro Kashiwakura
IPC分类号： H03L7/06 , H03D13/00 , H03L7/085
CPC分类号： H03L7/085 , H03D13/00 , H03K2005/00097 , H03K2005/00104 , H03L7/0812 , H03L7/089 , H03L7/091 , H03L7/10
摘要： A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock.
摘要翻译：相位检测范围能够扩展到参考时钟的周期的任意次数，并且在应用于DLL电路的情况下，能够自由选择操作周期。相位比较装置包括分频器，其产生通过接收参考时钟并将其除以2而获得的分频时钟; 反相器，其使分频时钟的相位反相以产生分频倒相时钟; DFF电路，其将分频反相时钟与延迟时钟同步以产生同步时钟; DFF电路，使时钟与反馈时钟同步以产生最终的同步时钟; 以及相位比较器，其接收除法时钟和最终同步时钟，以比较分频时钟和最终同步时钟的相位。

7. 发明申请

US20130009627A1 PHASE DETECTOR 有权
标题翻译：相位检测器
公开(公告)号：US20130009627A1
公开(公告)日：2013-01-10
申请号：US13636742
申请日：2010-03-25
申请人： Mingquan Bao
发明人： Mingquan Bao
IPC分类号： G01R25/00
CPC分类号： H03L7/085 , G01R25/005 , H03D13/00
摘要： A phase detector (100, 400, 800) comprising a balun (150) and input ports (116) at each of the balun's balanced ports. The phase detector (100, 400, 800) has four devices (105, 115, 110, 155) for measuring a signal's amplitude: —a first device (105) at a first input port (116), —a second device (115) at a second input port (117), —a third device (110) between the input ports (116, 117), connected to the ports via a passive component (120, 125; 120′, 125; 120″, 125″), —a fourth device (155) at the unbalanced port of the balun (150), The difference between the amplitude values of the third (110) and fourth (155) devices indicate the phase difference and the difference between the amplitude values measured by the first (110) and second (115) devices indicates the phase difference in the region of 0-2π.
摘要翻译：在每个平衡 - 不平衡转换器的平衡端口中包括平衡不平衡变换器（150）和输入端口（116）的相位检测器（100,400,800）。相位检测器（100,400,800）具有用于测量信号幅度的四个装置（105,115,110,155）：在第一输入端口（116）处的第一装置（105）， - 第二装置（115））在第二输入端口（117）处， - 在输入端口（116,117）之间的第三设备（110），经由无源部件（120,125; 120'，125; 120“，125”连接到端口））， - 平衡 - 不平衡变换器（150）的不平衡端口处的第四器件（155）。第三器件（110）和第四器件（155）的振幅值之间的差指示相位差和测量的振幅值之间的差通过第一（110）和第二（115）装置指示0-2＆pgr的区域中的相位差。

8. 发明授权

US08314620B2 Systems and methods for online phase calibration 有权
标题翻译：用于在线相位校准的系统和方法
公开(公告)号：US08314620B2
公开(公告)日：2012-11-20
申请号：US13150584
申请日：2011-06-01
申请人： Emad Andarawis Andarawis
发明人： Emad Andarawis Andarawis
IPC分类号： G01R25/00 , G01B7/00
CPC分类号： H03D13/00
摘要： A system for online relative phase calibration is provided. The system includes at least one excitation source configured to generate multiple excitation signals. The system also includes at least two sensors coupled to respective ones of the at least one excitation source via a transmission line, wherein the two sensors are configured to receive respective ones of the excitation signals. The system further includes at least two phase detectors configured to receive at least two reflected signals from the two sensors via the transmission line, wherein each of the two phase detectors are configured to output a respective voltage representing a phase difference between respective ones of the reflected signals and respective ones of the excitation signals. The system also includes a switch coupled to the sensors and the phase detectors, the switch configured to switch the phase detectors between the sensors at a pre-determined switching interval. The system further includes a calibration module coupled to the phase detectors, wherein the calibration module is configured to receive and process the respective voltage from the at least two phase detectors to generate respective calibrated voltage signals, wherein the calibration module is further configured to and match the calibrated voltage signals of each of the phase detectors.
摘要翻译：提供了一种在线相位校准系统。该系统包括被配置为产生多个激励信号的至少一个激励源。该系统还包括经由传输线耦合到至少一个激励源中的相应激励源的至少两个传感器，其中两个传感器被配置为接收相应的激励信号。该系统还包括至少两个相位检测器，其被配置为经由传输线从两个传感器接收至少两个反射信号，其中两个相位检测器中的每一个被配置为输出表示相应反射信号之间的相位差的相应电压信号和各个激励信号。该系统还包括耦合到传感器和相位检测器的开关，该开关被配置成以预定的切换间隔在传感器之间切换相位检测器。所述系统还包括耦合到所述相位检测器的校准模块，其中所述校准模块被配置为接收并处理来自所述至少两个相位检测器的相应电压以产生相应的校准电压信号，其中所述校准模块还被配置为并匹配每个相位检测器的校准电压信号。

9. 发明申请

US20120218001A1 Techniques for Phase Detection 审中-公开
标题翻译：相位检测技术
公开(公告)号：US20120218001A1
公开(公告)日：2012-08-30
申请号：US13505714
申请日：2010-10-31
申请人： Brian Leibowitz , Hae-Chang Lee , Farshid Aryanfar , Kun-Yung Chang , Jie Shen
发明人： Brian Leibowitz , Hae-Chang Lee , Farshid Aryanfar , Kun-Yung Chang , Jie Shen
IPC分类号： H03D13/00
CPC分类号： H03D13/00 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/085
摘要： A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.
摘要翻译：相位检测电路可以包括两个相位检测器，每个相位检测器响应于同相对准的输入信号而产生非零输出。输入信号基于两个周期信号。相位检测电路从另一相位检测器的输出信号中减去一相位检测器的输出信号，当周期信号同相时产生具有零值的信号。或者，相位检测器产生指示周期信号之间的相位差的相位比较信号。相位比较信号响应于相位检测器的相位输入信号具有非零值。输入信号基于周期信号。输出电路接收相位比较信号，并响应于同相对齐的周期信号产生具有零值的输出。

10. 发明授权

US08058915B2 Digital phase-locked loop and digital phase-frequency detector thereof 有权
标题翻译：数字锁相环及其数字相位检波器
公开(公告)号：US08058915B2
公开(公告)日：2011-11-15
申请号：US12550393
申请日：2009-08-30
申请人： Huan-Ke Chiu , Tzu-Chan Chueh
发明人： Huan-Ke Chiu , Tzu-Chan Chueh
IPC分类号： H03L7/06 , H03D13/00
CPC分类号： H03L7/085 , H03D13/00 , H03L7/0802 , H03L7/087 , H03L7/093 , H03L2207/50
摘要： A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.
摘要翻译：提供数字锁相环及其数字相位检波器。数字PFD包括除数开关单元，低分辨率相位误差检测单元，累积单元，高分辨率相位误差检测单元，恒定单元和选择器。除数开关单元接收并去除用于获得反馈时钟的反馈信号的部分脉冲。低分辨率相位误差检测单元检测参考信号和反馈时钟之间的相位误差，以获得相位误差脉冲宽度。累加单元在相位误差脉冲宽度期间积累反馈信号以获得输出选择信号。高分辨率相位误差检测单元检测参考信号和反馈信号之间的相位误差，以获得相位误差值。恒定单位提供至少一个常数值。选择器根据输出选择信号选择并输出相位误差值和常数值之一。

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