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1. 发明授权

US07609088B2 Programmable logic array 失效
标题翻译：可编程逻辑阵列
公开(公告)号：US07609088B2
公开(公告)日：2009-10-27
申请号：US11295634
申请日：2005-12-07
申请人： Dong-Gyu Lee
发明人： Dong-Gyu Lee
IPC分类号： H03K19/177
CPC分类号： H03K19/1772
摘要： A programmable logic array (PLA) which may include an AND-plane receiving first input signals and generating logic product signals based on the first input signals, and an OR-plane receiving the logic product signals and a second input signal and generating a logic sum signal based on the logic product signals.
摘要翻译：可编程逻辑阵列（PLA），其可以包括接收第一输入信号的AND平面和基于第一输入信号产生逻辑积信号的OR平面;以及接收逻辑积信号的OR平面和第二输入信号，并产生逻辑和信号基于逻辑产品信号。

2. 发明授权

US06708190B1 Reduced product term carry chain 有权
标题翻译：减少产品期限携带链
公开(公告)号：US06708190B1
公开(公告)日：2004-03-16
申请号：US09587708
申请日：2000-06-05
申请人： Christopher W. Jones , Roger Bettman
发明人： Christopher W. Jones , Roger Bettman
IPC分类号： G06F738
CPC分类号： G06F7/5443 , H03K19/1772
摘要： A programmable logic device comprising one or more macrocells and a product term array. The macrocells may comprise logic that may be configured to (i) generate and propagate a carry signal and (ii) generate a sum bit. The product term array may comprise two product terms per macrocell.
摘要翻译：一种包括一个或多个宏小区和产品项阵列的可编程逻辑设备。宏小区可以包括可以被配置为（i）生成和传播进位信号的逻辑，并且（ii）生成和位。产品术语阵列可以包括每个宏单元的两个乘积项。

3. 发明授权

US06222383B1 Controlled PMOS load on a CMOS PLA 失效
标题翻译： CMOS PLA上的受控PMOS负载
公开(公告)号：US06222383B1
公开(公告)日：2001-04-24
申请号：US08773136
申请日：1996-12-26
申请人： David Minoru Murata , Mark Ronald Santoro , Lee Stuart Tavrow
发明人： David Minoru Murata , Mark Ronald Santoro , Lee Stuart Tavrow
IPC分类号： H03K19094
CPC分类号： H03K19/1772
摘要： A programmable logic array (PLA) AND plane receives data input signals from input registers and generates corresponding minterms. The minterms are OR-ed together to form a sum of products, which are provided to output latches and clocked out before the end of each clock cycle by an internal self-timed signal as PLA output data. The OR plane (or the AND plane, or both) includes NOR gates that include a plurality of NMOS transistors. Each NMOS transistor in a gate has its drain connected to a common NOR gate output node, its source connected to ground and its gate connected to receive a corresponding minterm from the AND plane. The NOR gate further includes a PMOS load transistor having its source connected to a voltage supply, its drain connected to the NOR gate output node and its gate connected to receive a timing signal that turns on the PMOS load transistor as the minterms are generated at the output of the AND plane and turns off the PMOS load transistor when the sum of products are provided at the output latches.
摘要翻译：可编程逻辑阵列（PLA）AND平面从输入寄存器接收数据输入信号并产生相应的minterms。这些节点被组合在一起形成一个产品的总和，它们被提供给输出锁存器，并且在每个时钟周期结束之前通过作为PLA输出数据的内部自定时信号被计时。 OR平面（或AND平面，或两者）包括包括多个NMOS晶体管的NOR门。栅极中的每个NMOS晶体管的漏极连接到公共或非门输出节点，其源极连接到地，其栅极连接以从AND平面接收相应的最小值。或非门还包括PMOS负载晶体管，其源极连接到电压源，其漏极连接到或非门输出节点，其栅极连接以接收定时信号，该定时信号导通PMOS负载晶体管，因为在输出AND平面，并在输出锁存器处提供产品总和时关断PMOS负载晶体管。

4. 发明授权

US5634061A Instruction decoder utilizing a low power PLA that powers up both AND and OR planes only when successful instruction fetch signal is provided 失效
标题翻译：只有当提供成功的指令提取信号时，才使用低功率PLA的指令解码器为AND和OR平面供电
公开(公告)号：US5634061A
公开(公告)日：1997-05-27
申请号：US232405
申请日：1994-04-25
申请人： Atsushi Horie , Tohru Utsumi
发明人： Atsushi Horie , Tohru Utsumi
IPC分类号： G06F1/32 , G06F1/26 , G06F9/30 , H03K19/00 , H03K19/177
CPC分类号： H03K19/0016 , H03K19/17708 , H03K19/1772
摘要： Disclosed is a programmable logic array (PLA), comprising an AND plane comprising a plurality of input lines and a plurality of product term lines crossing the input lines, an OR plane comprising the product term lines and a plurality of output lines crossing the product term lines, a power source VDD providing an electrical power to the AND and OR planes, and control line for controlling the supply of the electric power to the AND and OR planes, wherein the electrical power from the power source VDD is provided to the PLA when a signal indicating the use of the PLA is provided to the control line, and the supply of the electrical power from the power source VDD to the PLA is stopped on receipt of a signal designating that the PLA is in the unused state. In addition, various data processing systems incorporating the PLA are disclosed.
摘要翻译：公开了一种可编程逻辑阵列（PLA），包括AND平面，其包括多个输入线和与输入线交叉的多个乘积项; OR平面，包括乘积项线和与产品项交叉的多个输出线线路，向AND和OR平面提供电力的电源VDD以及用于控制向AND和OR平面供电的控制线，其中来自电源VDD的电力被提供给PLA，指示使用PLA的信号被提供给控制线，并且在接收到指示PLA处于未使用状态的信号时，停止从电源VDD到PLA的电力供应。另外，公开了包含PLA的各种数据处理系统。

5. 发明授权

US5101122A Programmable logic device 失效
标题翻译：可编程逻辑器件
公开(公告)号：US5101122A
公开(公告)日：1992-03-31
申请号：US616276
申请日：1990-11-20
申请人： Hirofumi Shinonara
发明人： Hirofumi Shinonara
IPC分类号： H03K19/177
CPC分类号： H03K19/1772
摘要： A programmable logic device includes AND-plane and OR-plane. The AND-plane includes first input signal lines (B1, B1, B2, B2) having input signals transmitted, product term lines (A1-A4), a first precharge circuit (3b), a clock generator (15) for generating a first clock signal, and a dummy circuit (7b) having dummy output lines which have the precharge finished in response to the first clock signal and the discharge made at a speed less than the slowest discharge speed of the product term lines. The OR-plane includes second input signal lines (AB1-AB4), sum term lines (01-04), dummy input lines (ADB1, ADB2) to be charged at a speed less than the lowest charge speed of the second input signal lines, and second precharge circuit (5b). The programmable logic device further includes a second clock generator (8c; 8d; 8e) for generating a second clock signal and circuitry (16) for generating a third clock signal in response to the external clock, and circuitry (L1-L4) for latching the signal potential on the sum term lines so as to derive the output signals. The respective two sum lines are arranged in a pair, and one discharge signal line (CD1-CD4) is provided to the pair.
摘要翻译：可编程逻辑器件包括AND平面和OR平面。 AND平面包括具有发送的输入信号的第一输入信号线（B1，B1，B2，B2），乘积项线（A1-A4），第一预充电电路（3b），时钟发生器（15）时钟信号，以及具有响应于第一时钟信号而预充电结束的虚拟输出线和以低于产品项线的最慢放电速度的速度进行放电的虚拟电路（7b）。 OR平面包括以比第二输入信号线的最低充电速度小的速度充电的第二输入信号线（AB1-AB4），总和项线（01-04），虚拟输入线（ADB1，ADB2）和第二预充电电路（5b）。可编程逻辑器件还包括用于产生第二时钟信号的第二时钟发生器（8c; 8d; 8e）和用于响应于外部时钟产生第三时钟信号的电路（16），以及用于锁存的电路（L1-L4）总和项线上的信号电位，以便导出输出信号。相应的两条总和线成对配置，并且一对放电信号线（CD1-CD4）被提供。

6. 发明授权

US5033017A Programmable logic array with reduced power consumption 失效
标题翻译：可编程逻辑阵列，功耗降低
公开(公告)号：US5033017A
公开(公告)日：1991-07-16
申请号：US333939
申请日：1989-04-06
申请人： Takayoshi Taniai , Tadashi Saitoh , Yasuhiro Tanaka
发明人： Takayoshi Taniai , Tadashi Saitoh , Yasuhiro Tanaka
IPC分类号： G06F7/00 , G06F1/04 , H03K19/00 , H03K19/177
CPC分类号： H03K19/0016 , H03K19/1772
摘要： A programmable logic array includes a programmable logic array being precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto. The programmable logic array also includes a circuit connected to the programmable logic array, for holding the programmable logic array in a precharged state by setting the clock signal to a fixed level when the programmable logic array is not selected and for switching the programmable logic array to a discharged state by supplying the clock signal the programmable logic array when the programmable logic array is selected, so that the programmable logic array is discharged on the basis of the contents of the input data when selected.

7. 发明授权

US4886987A Programmable logic array with 2-bit input partitioning 失效
标题翻译：具有2位输入分区的可编程逻辑阵列
公开(公告)号：US4886987A
公开(公告)日：1989-12-12
申请号：US192767
申请日：1988-05-11
申请人： Kimiyoshi Usami
发明人： Kimiyoshi Usami
IPC分类号： H03K19/177 , H03M7/00
CPC分类号： H03K19/1772 , H03M7/005
摘要： A programmable logic array comprises an input decoder having a plurality of paired first transistors inputting signals and connected in series to each other, the input decoder outputting predetermined logic signals through the first transistors based on the input signals and inverted input signals thereof; second transistors for supplying the logic output signals of the input decoder to corresponding input lines in an AND array region; and third transistors for predischarging the input lines of the AND array region.
摘要翻译：可编程逻辑阵列包括输入解码器，其具有输入信号并彼此串联连接的多个成对第一晶体管，输入解码器基于输入信号及其反相输入信号通过第一晶体管输出预定逻辑信号; 第二晶体管，用于将输入解码器的逻辑输出信号提供给AND阵列区域中的对应输入线; 以及用于对AND阵列区域的输入线进行预充电的第三晶体管。

8. 发明授权

US4764691A CMOS programmable logic array using NOR gates for clocking 失效
标题翻译： CMOS可编程逻辑阵列使用NOR门进行时钟控制
公开(公告)号：US4764691A
公开(公告)日：1988-08-16
申请号：US787234
申请日：1985-10-15
申请人： Daniel R. Jochem
发明人： Daniel R. Jochem
IPC分类号： H01L21/82 , G06F15/78 , H03K19/00 , H03K19/096 , H03K19/173 , H03K19/177
CPC分类号： H03K19/0013 , H03K19/1772
摘要： A programmable logic array 100 which uses parallel transistor logic gates 150 arranged in a compact layout for fast signal propagation. One of logic planes 120 or 130 is prechargeable to substantially reduce power consumption using a simple, one-phase clock.
摘要翻译：一种可编程逻辑阵列100，其使用以紧凑布局布置的并行晶体管逻辑门150，用于快速信号传播。逻辑平面120或130之一可预充电，以便使用简单的单相时钟来显着降低功耗。

9. 发明授权

US4636661A Ratioless FET programmable logic array 失效
标题翻译：无限FET可编程逻辑阵列
公开(公告)号：US4636661A
公开(公告)日：1987-01-13
申请号：US684638
申请日：1984-12-21
申请人： Syed T. Mahmud
发明人： Syed T. Mahmud
IPC分类号： H03K19/177 , H03K19/20 , H03K19/003 , H03K19/094
CPC分类号： H03K19/1772
摘要： A ratioless, zero d.c. power dissipating FET programmable logic array including a column boost capacitor for maintaining the columns of selected AND array transistors at approximately their precharged voltage while their associated OR array transistors are being evaluated.
摘要翻译：无痛，零直流功率耗散FET可编程逻辑阵列，包括列升压电容器，用于将所选择的AND阵列晶体管的列保持在大约其预充电电压，同时对其相关联的OR阵列晶体管进行评估。

10. 发明授权

US4611133A High speed fully precharged programmable logic array 失效
标题翻译：高速全预充电可编程逻辑阵列
公开(公告)号：US4611133A
公开(公告)日：1986-09-09
申请号：US493901
申请日：1983-05-12
申请人： Benjamin C. Peterson , Yoseph L. Linde , Yigal Brandman
发明人： Benjamin C. Peterson , Yoseph L. Linde , Yigal Brandman
IPC分类号： H03K19/177 , H03K19/017 , H03K19/096 , H03K19/20
CPC分类号： H03K19/1772
摘要： A logic array which is small in size and low in power dissipation uses only one clock signal. The array is fully precharged by precharging a first portion and a second portion and then applying ground to the first portion while delayably applying the ground to the second portion. The address is read into the first portion during the precharging to speed up operation of the array.
摘要翻译：体积小，功耗低的逻辑阵列仅使用一个时钟信号。通过对第一部分和第二部分进行预充电然后将接地施加到第一部分同时将接地延伸到第二部分来将阵列完全预充电。在预充电期间将地址读入第一部分以加速阵列的操作。

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