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1. 发明申请

US20170245325A1 Intelligently Powered Devices 审中-公开
公开(公告)号：US20170245325A1
公开(公告)日：2017-08-24
申请号：US15405264
申请日：2017-01-12
申请人： John Arthur Fee , Louis F. Perez
发明人： John Arthur Fee , Louis F. Perez
IPC分类号： H05B3/36 , B60N2/56 , A47C7/74 , H03K9/06 , H03K9/08
CPC分类号： H05B3/36 , A47C7/748 , B60N2/5685 , H03K9/06 , H03K9/08 , H05B1/0238 , H05B3/04 , H05B2203/029 , H05B2203/032 , H05B2203/036
摘要： A device, such as a heated seat cushion device, is provided. Circuitry and other components are used to regulate, control and/or switch electrical power to an electrical element, such as a heating element, of the device. The device may regulate the energy delivered to the electrical element by a processor on an intelligent energy management platform. Accordingly, power may be routed to the electrical element of the heated device in a controlled manner. Control may include turning on and off the power, providing pulsed power, and modulating the power and/or pulsed power delivered to the electrical element.

2. 发明申请

US20170244584A1 TIME DOMAIN SYMBOL RECEIVER 审中-公开
公开(公告)号：US20170244584A1
公开(公告)日：2017-08-24
申请号：US15588619
申请日：2017-05-06
申请人： Lightfleet Corporation
发明人： William B Dress
IPC分类号： H04L25/49
CPC分类号： H04L25/4902 , H03K7/08 , H03K9/08
摘要： Methods and apparatus are described for time domain signals. An apparatus includes an electrical circuit decoder coupled to a receiver.

3. 发明申请

US20170040981A1 SEQUENCED PULSE-WIDTH ADJUSTMENT IN A RESONANT CLOCKING CIRCUIT 有权
标题翻译：谐振时钟电路中的顺序脉冲宽度调整
公开(公告)号：US20170040981A1
公开(公告)日：2017-02-09
申请号：US14828841
申请日：2015-08-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Phillip J. Restle , David Wen-Hao Shan
IPC分类号： H03K3/012 , G06F1/10 , H03K9/08
CPC分类号： H03K3/012 , G06F1/08 , G06F1/10 , H03K5/06 , H03K7/08 , H03K9/08
摘要： A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
摘要翻译：用于谐振时钟分配网络的时钟驱动器控制方案通过控制驱动谐振时钟分配网络的时钟驱动器电路的输出的脉冲宽度来提供鲁棒的操作，使得改变被排序。时钟驱动器控制电路通过提供给对应的时钟驱动器电路的多个控制信号，根据所选择的操作模式控制相应扇区中的时钟驱动器电路。在具有耦合到谐振时钟分配网络的时钟输入的集成电路内的数字电路的操作期间，至少一些扇区的脉冲宽度不同。不同的脉冲宽度可以是响应于向时钟驱动器电路提供输入的全局时钟的模式或频率变化而施加的瞬态差异。

4. 发明授权

US09444439B2 Pulse generating circuit for audio-frequency amplifiers and regulated power supplies 有权
标题翻译：用于音频放大器和稳压电源的脉冲发生电路
公开(公告)号：US09444439B2
公开(公告)日：2016-09-13
申请号：US14397819
申请日：2013-04-30
申请人： INDICE SEMICONDUCTOR INC.
发明人： James Hamond
IPC分类号： H03K5/01 , H03K7/08 , H03K9/08 , H03F3/217 , H02M1/08 , H03K5/02
CPC分类号： H03K5/01 , H02M1/08 , H03F3/2173 , H03K5/02 , H03K7/08 , H03K9/08
摘要： A circuit for generating a series of pulses in response to a first signal, the circuit comprising: a lossy integrator which receives a second signal as its input; and a comparator which: receives the output of the lossy integrator at one of its inputs; and receives the first signal at the other of its inputs. This circuit can be incorporated into, for example, audio-frequency amplifiers and regulated power supplies.
摘要翻译：一种用于响应于第一信号产生一系列脉冲的电路，所述电路包括：有损收集器，其接收第二信号作为其输入; 以及比较器，其在其输入之一处接收有损积分器的输出; 并在其另一个输入端接收第一个信号。该电路可以结合到例如音频放大器和稳压电源中。

5. 发明授权

US09172394B2 Signal conversion system and method 有权
标题翻译：信号转换系统及方法
公开(公告)号：US09172394B2
公开(公告)日：2015-10-27
申请号：US14382979
申请日：2013-03-06
申请人： Actiwave AB
发明人： Erik Lindahl , Pär Gunnars Risberg
IPC分类号： H03M5/08 , H03K9/08 , H03M3/00 , H04L25/49 , H03K7/08
CPC分类号： H03K7/08 , H03K9/08 , H03M3/506 , H03M5/08 , H04L25/4902
摘要： A signal conversion system and method for converting an input signal to a pulse width modulated signal is disclosed. The signal conversion system includes a sample rate converter coupled with an associated pulse width modulation (PWM) module. A hardware and power efficient signal conversion system for resampling an audio input signal with an arbitrary sample rate to a pulse width modulated output audio signal for use in an audio processor and/or reproduction is disclosed. The signal conversion system may be particularly suitable for use in a battery operated consumer electronics device.
摘要翻译：公开了一种用于将输入信号转换为脉宽调制信号的信号转换系统和方法。信号转换系统包括与相关联的脉宽调制（PWM）模块耦合的采样率转换器。公开了一种硬件和功率有效的信号转换系统，用于将具有任意采样率的音频输入信号重新采样到用于音频处理器和/或再现的脉宽调制输出音频信号。信号转换系统可能特别适用于电池供电的消费电子设备。

6. 发明申请

US20150303910A1 PULSE-WIDTH MODULATION DATA DECODER 有权
标题翻译：脉冲宽度调制数据解码器
公开(公告)号：US20150303910A1
公开(公告)日：2015-10-22
申请号：US14258980
申请日：2014-04-22
申请人： QUALCOMM Incorporated
发明人： Zhi Zhu , Xiaohua Kong , Li Sun , Jie Xu
IPC分类号： H03K9/08
CPC分类号： H03K9/08 , G06F13/4072 , H04L25/4902 , Y02D10/14 , Y02D10/151
摘要： Systems and methods for decoding pulse-width modulated (PWM) data are disclosed. An example decoder filters a data input signal with a one-sided pulse filter. The one-sided pulse filter suppresses short pulses on the data input signal and passes long pulses. The example decoder latch the filtered data signal at the end of each bit time of the data input signal. The duration of pulses that are suppressed by the one-sided pulse filter can be calibrated to compensate for circuit variations and to allow the decoder to operate at various data rates. The decoder can be implemented in a small integrated circuit area and can be power efficient.
摘要翻译：公开了用于解码脉宽调制（PWM）数据的系统和方法。示例解码器用单向脉冲滤波器对数据输入信号进行滤波。单面脉冲滤波器抑制数据输入信号的短脉冲，并通过长脉冲。示例解码器在数据输入信号的每个位时间结束时锁存经滤波的数据信号。由单侧脉冲滤波器抑制的脉冲的持续时间可被校准，以补偿电路变化并允许解码器以各种数据速率工作。解码器可以在小的集成电路区域中实现，并且可以是功率效率的。

7. 发明申请

US20150295589A1 CONVERTING TIME-ENCODED SIGNAL INTO ANALOG OUTPUT 有权
标题翻译：将时间编码的信号转换为模拟输出
公开(公告)号：US20150295589A1
公开(公告)日：2015-10-15
申请号：US14669508
申请日：2015-03-26
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Daniel James Eddleman , Chad Thomas Steward
IPC分类号： H03M1/82
CPC分类号： H03M1/822 , H03K9/08
摘要： A converter may generate an analog output that is representative of a time-encoded signal. The circuit may include an input port receiving the time-encoded signal; a time-encoded to digital converter coupled to the input port; and a digital-to-analog converter coupled to the time-encoded to digital converter.
摘要翻译： A转换器可以产生代表时间编码信号的模拟输出。电路可以包括接收时间编码信号的输入端口; 耦合到输入端口的时间编码到数字转换器; 以及耦合到时间编码到数字转换器的数模转换器。

8. 发明申请

US20140361829A1 SYSTEM AND METHOD FOR PULSE WIDTH MODULATION 有权
标题翻译：脉宽调制系统与方法
公开(公告)号：US20140361829A1
公开(公告)日：2014-12-11
申请号：US14298428
申请日：2014-06-06
申请人： Texas Instruments
发明人： Sumantra Seth , Utlam Kumar Patro , Jagdish Chand Goyal , 8iman Chattopadhyay
IPC分类号： H03K9/08
CPC分类号： H03K9/08
摘要： A circuit for use with PWM signal having first pulse and a second pulse, wherein the first pulse has a period and a first duty cycle, and the second pulse has the period and a second duty cycle. The period has clock information therein, the first duty cycle has first data information therein, and the second duty cycle has second data information therein. The circuit includes a first integrating component and a second integrating component. The first integrating component can generate a first voltage corresponding to the first duty cycle and a second voltage corresponding to the first duty cycle. The second integrating component can generate a third voltage corresponding to the second duty cycle and a fourth voltage corresponding to the second duty cycle.
摘要翻译：一种与具有第一脉冲和第二脉冲的PWM信号一起使用的电路，其中所述第一脉冲具有周期和第一占空比，并且所述第二脉冲具有所述周期和第二占空比。该周期具有时钟信息，第一占空比在其中具有第一数据信息，第二占空比在其中具有第二数据信息。电路包括第一积分元件和第二积分元件。第一积分分量可以产生对应于第一占空比的第一电压和对应于第一占空比的第二电压。第二积分分量可以产生对应于第二占空比的第三电压和对应于第二占空比的第四电压。

9. 发明申请

US20110068770A1 Method for Determining the Offset of a Periodic Signal 有权
标题翻译：确定周期信号偏移的方法
公开(公告)号：US20110068770A1
公开(公告)日：2011-03-24
申请号：US12993286
申请日：2009-05-11
申请人： Jalal Hallak
发明人： Jalal Hallak
IPC分类号： G01R25/00
CPC分类号： H03K9/08 , G01R19/0015
摘要： A method for determining the offset of a periodic signal is provided, wherein an offset value that is caused by a level change of the periodic signal is suppressed.
摘要翻译：提供一种用于确定周期性信号的偏移的方法，其中由周期信号的电平变化引起的偏移值被抑制。

10. 发明申请

US20100172400A1 ADAPTIVE EQUALIZATION APPARATUS WITH EQUALIZATION PARAMETER SETTING ADPATIVELY ADJUSTED ACCORDING TO EDGES OF EQUALIZER OUTPUT MONITORED IN REAL-TIME MANNER AND RELATED METHOD THEREOF 有权
标题翻译：具有均衡参数设置的自适应均衡设备根据实时监控的均衡器输出边缘进行调整和相关方法
公开(公告)号：US20100172400A1
公开(公告)日：2010-07-08
申请号：US12350193
申请日：2009-01-07
申请人： Min-Chung Chou
发明人： Min-Chung Chou
IPC分类号： H03K5/159 , H04L7/02
CPC分类号： H04L7/0058 , H03K9/08 , H04L25/03019
摘要： An adaptive equalization apparatus is provided. The adaptive equalization apparatus includes an equalizer, a monitor circuit, and a control circuit. The equalizer receives a first signal, and equalizes the first signal according to an equalization parameter setting to thereby generate a second signal. The monitor circuit is electrically connected to the equalizer, and monitors edges of the second signal in a real-time manner to thereby generate a detection result. The control logic is electrically connected to the equalizer, and adaptively adjusts the equalization parameter setting according to the detection result.
摘要翻译：提供一种自适应均衡装置。自适应均衡装置包括均衡器，监视电路和控制电路。均衡器接收第一信号，并根据均衡参数设置对第一信号进行均衡，从而产生第二信号。监视电路电连接到均衡器，并且以实时的方式监视第二信号的边缘，从而产生检测结果。控制逻辑电连接到均衡器，并且根据检测结果自适应地调整均衡参数设置。

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