专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10038455B2 Signal modulation for radiofrequency communications 有权
公开(公告)号：US10038455B2
公开(公告)日：2018-07-31
申请号：US15308216
申请日：2014-05-05
申请人： Alcatel Lucent
发明人： Luc Dartois
IPC分类号： H03M3/00 , H04B1/04 , H03F3/19 , H03F3/24 , H03F1/32
CPC分类号： H03M3/402 , H03F1/3241 , H03F3/189 , H03F3/19 , H03F3/217 , H03F3/24 , H03F3/245 , H03F2200/451 , H03F2201/3233 , H03M3/41 , H03M3/504 , H03M3/506 , H04B1/04 , H04B1/0475 , H04B2001/0408 , H04B2001/045
摘要： A signal modulation device comprising: an input for receiving a complex input signal (106) comprising an in-phase component signal and a quadrature-phase component signal, a sigma-delta modulator (110) for modulating the complex input signal at an oversampling clock rate (F1) into an intermediary signal (112), a numerical oscillator (60) for generating a phase signal (61) oscillating at a selected carrier frequency (FC), wherein the phase signal takes a finite number of quantized states, and a symbol mapping table (114) comprising a predefined quantized symbol for each quantized complex state of the intermediary signal and each quantized state of the phase signal, and operates at each oversampling clock period (F1) to select a quantized symbol (116) as a function of a current quantized complex state of the intermediary signal (112) and a current quantized state of the phase signal (61).

2. 发明申请

US20170317686A1 SIGNAL MODULATION FOR RADIOFREQUENCY COMMUNICATIONS 审中-公开
公开(公告)号：US20170317686A1
公开(公告)日：2017-11-02
申请号：US15308216
申请日：2014-05-05
申请人： ALCATEL LUCENT
发明人： Luc Dartois
IPC分类号： H03M3/00 , H03F3/24 , H04B1/04 , H03F1/32 , H03F3/19
CPC分类号： H03M3/402 , H03F1/3241 , H03F3/189 , H03F3/19 , H03F3/217 , H03F3/24 , H03F3/245 , H03F2200/451 , H03F2201/3233 , H03M3/41 , H03M3/504 , H03M3/506 , H04B1/04 , H04B1/0475 , H04B2001/0408 , H04B2001/045
摘要： A signal modulation device comprising: an input for receiving a complex input signal (106) comprising an in-phase component signal and a quadrature-phase component signal, a sigma-delta modulator (110) for modulating the complex input signal at an oversampling clock rate (F1) into an intermediary signal (112), a numerical oscillator (60) for generating a phase signal (61) oscillating at a selected carrier frequency (FC), wherein the phase signal takes a finite number of quantized states, and a symbol mapping table (114) comprising a predefined quantized symbol for each quantized complex state of the intermediary signal and each quantized state of the phase signal, and operates at each oversampling clock period (F1) to select a quantized symbol (116) as a function of a current quantized complex state of the intermediary signal (112) and a current quantized state of the phase signal (61).

3. 发明授权

US09503070B2 Signal conversion system and method 有权
公开(公告)号：US09503070B2
公开(公告)日：2016-11-22
申请号：US14920089
申请日：2015-10-22
申请人： Actiwave AB
发明人： Erik Lindahl , Pär Gunnars Risberg
IPC分类号： H03K7/08 , H03K9/08 , H03M3/00 , H04L25/49 , H03M5/08
CPC分类号： H03K7/08 , H03K9/08 , H03M3/506 , H03M5/08 , H04L25/4902
摘要： A signal conversion system and method for converting an input signal to a pulse width modulated signal is disclosed. The signal conversion system includes a sample rate converter coupled with an associated pulse width modulation (PWM) module. A hardware and power efficient signal conversion system for resampling an audio input signal with an arbitrary sample rate to a pulse width modulated output audio signal for use in an audio processor and/or reproduction is disclosed. The signal conversion system may be particularly suitable for use in a battery operated consumer electronics device.

4. 发明授权

US08988263B2 Successive approximation register (SAR) analog-to-digital converter (ADC) having optimized filter 有权
标题翻译：具有优化滤波器的逐次逼近寄存器（SAR）模数转换器（ADC）
公开(公告)号：US08988263B2
公开(公告)日：2015-03-24
申请号：US13562729
申请日：2012-07-31
申请人： Sanyi Zhan , Daniel J. Cooley , Ligang Zhang
发明人： Sanyi Zhan , Daniel J. Cooley , Ligang Zhang
IPC分类号： H03M1/12 , H03M1/46 , H03M3/00
CPC分类号： H03M1/46 , H03M3/506
摘要： A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path.
摘要翻译：诸如机械调谐无线电的系统可以具有用于接收和处理输入射频（RF）信号的信号路径，并且将经处理的信号提供给第一模数转换器（ADC）以将处理的信号转换为并且数字解调数字信号以获得音频信号，其中该第一ADC与辅助ADC分离而不是信号路径的一部分。

5. 发明申请

US20150015426A1 SIGNAL CONVERSION SYSTEM AND METHOD 有权
标题翻译：信号转换系统和方法
公开(公告)号：US20150015426A1
公开(公告)日：2015-01-15
申请号：US14382979
申请日：2013-03-06
申请人： Actiwave AB
发明人： Erik Lindahl , Pär Gunnars Risberg
IPC分类号： H03M5/08
CPC分类号： H03K7/08 , H03K9/08 , H03M3/506 , H03M5/08 , H04L25/4902
摘要： A signal conversion system and method for converting an input signal to a pulse width modulated signal is disclosed. The signal conversion system includes a sample rate converter coupled with an associated pulse width modulation (PWM) module. A hardware and power efficient signal conversion system for resampling an audio input signal with an arbitrary sample rate to a pulse width modulated output audio signal for use in an audio processor and/or reproduction is disclosed. The signal conversion system may be particularly suitable for use in a battery operated consumer electronics device.
摘要翻译：公开了一种用于将输入信号转换为脉宽调制信号的信号转换系统和方法。信号转换系统包括与相关联的脉宽调制（PWM）模块耦合的采样率转换器。公开了一种硬件和功率有效的信号转换系统，用于将具有任意采样率的音频输入信号重新采样到用于音频处理器和/或再现的脉宽调制输出音频信号。信号转换系统可能特别适用于电池供电的消费电子设备。

6. 发明授权

US08912833B2 Device and method for pulse width modulation 有权
标题翻译：用于脉宽调制的装置和方法
公开(公告)号：US08912833B2
公开(公告)日：2014-12-16
申请号：US11673021
申请日：2007-02-09
申请人： Christoph Braun
发明人： Christoph Braun
IPC分类号： H03K3/017 , H04L25/49 , H03F3/217 , H03K7/08 , H03M3/00
CPC分类号： H03K7/08 , H03F3/217 , H03F2200/331 , H03F2200/351 , H03M3/506 , H04L25/4902
摘要： A device and a method for pulse width modulation is disclosed, wherein the temporal occurrence of both the respectively rising and the respectively falling edges of a pulse signal is varied.
摘要翻译：公开了一种用于脉冲宽度调制的装置和方法，其中脉冲信号的分别上升沿和下降沿两者的时间出现是变化的。

7. 发明授权

US08638242B2 Digital power management using serial data transfer 有权
标题翻译：数字电源管理采用串行数据传输
公开(公告)号：US08638242B2
公开(公告)日：2014-01-28
申请号：US13277662
申请日：2011-10-20
申请人： Paul Latham , Stewart Kenly
发明人： Paul Latham , Stewart Kenly
IPC分类号： H03M7/00
CPC分类号： H03M3/344 , H03M3/328 , H03M3/506
摘要： Methods and systems for digital control utilizing oversampling.
摘要翻译：使用过采样的数字控制方法和系统。

8. 发明申请

US20110102223A1 AMPLIFIER WITH DIGITAL INPUT AND DIGITAL PWM CONTROL LOOP 有权
标题翻译：带数字输入和数字PWM控制环的放大器
公开(公告)号：US20110102223A1
公开(公告)日：2011-05-05
申请号：US12892487
申请日：2010-09-28
申请人： Martin Kinyua , Eric Soenen
发明人： Martin Kinyua , Eric Soenen
IPC分类号： H03M3/00
CPC分类号： H03M3/344 , H03F3/217 , H03M3/506
摘要： A class D amplifier is configured to accept a digital input signal wherein the control loop of the class D amplifier employs a hybrid filter merged with the front-end of a sigma-delta ADC converter. The term hybrid refers to the filter using both digital and analog components in which the digital delay elements serve as shift registers while the filter coefficients are analog. The filter converts the digital PDM data into a step-wise sinusoidal signal. The sigma-delta ADC receiving a feedback signal subtracts the step-wise sinusoidal signal from the continuous sinusoidal signal and converts the result to a digital PDM signal, without decimation, which passes through a digital filter, a PWM generator, and a pre-driver, to provide power to the load.
摘要翻译： D类放大器被配置为接受数字输入信号，其中D类放大器的控制环采用与Σ-ΔADC转换器的前端并入的混合滤波器。术语混合是指使用数字和模拟组件的滤波器，其中数字延迟元件用作移位寄存器，而滤波器系数是模拟的。滤波器将数字PDM数据转换成逐级正弦信号。接收反馈信号的Σ-ΔADC从连续正弦信号中减去逐级正弦信号，并将结果转换成数字PDM信号，而不抽抽，其通过数字滤波器，PWM发生器和预驱动器，为负载提供电力。

9. 发明授权

US07903015B1 Cascaded DAC architecture with pulse width modulation 有权
标题翻译：具有脉冲宽度调制的级联DAC架构
公开(公告)号：US07903015B1
公开(公告)日：2011-03-08
申请号：US12546521
申请日：2009-08-24
申请人： Rahmi Hezar , Lars Risbo
发明人： Rahmi Hezar , Lars Risbo
IPC分类号： H03M1/82
CPC分类号： H03M3/506 , H03M3/416 , H03M3/504
摘要： An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at an analog output of the cascaded circuit. Each of the cascade circuits contains a noise-shaping circuit, a PCM (Pulse Code Modulation)-to-PWM (Pulse Width Modulation) converter and a 1-bit P-tap AFIR (Analog Finite Impulse Response) filter DAC. Noise at the output of the cascaded circuit may be further reduced by increasing the number of cascade circuits.
摘要翻译：本发明的实施例提供了一个或多个级联在一起以形成级联电路的级联电路。级联电路降低级联电路模拟输出的噪声。每个级联电路包含噪声整形电路，PCM（脉冲编码调制）到PWM（脉宽调制）转换器和1位P抽头AFIR（模拟有限脉冲响应）滤波器DAC。可以通过增加级联电路的数量来进一步减少级联电路的输出端的噪声。

10. 发明申请

US20110043398A1 CASCADED DAC ARCHITECTURE WITH PULSE WIDTH MODULATION 有权
标题翻译：具有脉冲宽度调制的CASCADED DAC架构
公开(公告)号：US20110043398A1
公开(公告)日：2011-02-24
申请号：US12546521
申请日：2009-08-24
申请人： Rahmi Hezar , Lars Risbo
发明人： Rahmi Hezar , Lars Risbo
IPC分类号： H03M3/00
CPC分类号： H03M3/506 , H03M3/416 , H03M3/504
摘要： An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at an analog output of the cascaded circuit. Each of the cascade circuits contains a noise-shaping circuit, a PCM (Pulse Code Modulation)-to-PWM (Pulse Width Modulation) converter and a 1-bit P-tap AFIR (Analog Finite Impulse Response) filter DAC. Noise at the output of the cascaded circuit may be further reduced by increasing the number of cascade circuits.
摘要翻译：本发明的实施例提供了一个或多个级联在一起以形成级联电路的级联电路。级联电路降低级联电路模拟输出的噪声。每个级联电路包含噪声整形电路，PCM（脉冲编码调制）到PWM（脉宽调制）转换器和1位P抽头AFIR（模拟有限脉冲响应）滤波器DAC。可以通过增加级联电路的数量来进一步减少级联电路的输出端的噪声。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式