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1. 发明申请

US20100102894A1 DIGITALLY CONTROLLED OSCILLATOR WITH IMPROVED DIGITAL FREQUENCY CALIBRATION 失效
标题翻译：具有改进数字频率校准的数字控制振荡器
公开(公告)号：US20100102894A1
公开(公告)日：2010-04-29
申请号：US12366576
申请日：2009-02-05
申请人： Bo Sun , Zixiang Yang
发明人： Bo Sun , Zixiang Yang
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03B5/1265 , H03J1/0008 , H03J2200/10 , H03L7/10 , H03L2207/06 , H03L2207/50 , H03M1/1019 , H03M1/1042 , H03M1/1047 , H03M1/682 , H03M1/86
摘要： Techniques for calibrating digitally controlled oscillators (DCOS) are disclosed. In one aspect of the disclosure, an initial set of control codes for operating the DCO with a coarse frequency tuning bank with multiple overlapping coarse frequency tuning segments (LTBs) and one fine main frequency tuning bank (MTB) is determined. A range of output frequencies produced from the initial set is identified. Instances of overlap are identified in the frequency range between consecutive LTB segments. An offset in the MTB is added that corresponds to the overlap instance between consecutive LTBs to establish a revised set. The revised control codes are utilized to tune the DCO over the desired frequency range.
摘要翻译：公开了用于校准数字控制振荡器（DCOS）的技术。在本公开的一个方面，确定用于利用具有多个重叠粗调频调谐段（LTB）和一个精细主频调谐组（MTB）的粗调频调谐组操作DCO的初始控制码组。识别从初始集合产生的输出频率范围。在连续的LTB段之间的频率范围内识别重叠实例。添加MTB中的偏移量，其对应于连续LTB之间的重叠实例，以建立修订集。修改后的控制代码用于在期望的频率范围内调谐DCO。

2. 发明申请

US20090295614A1 DIGITAL-TO-ANALOG CONVERTER CIRCUIT LAYOUT 有权
标题翻译：数字到模拟转换器电路布局
公开(公告)号：US20090295614A1
公开(公告)日：2009-12-03
申请号：US12475112
申请日：2009-05-29
申请人： Laurent Avon , Reiner Bidenbach , Klaus Heberle
发明人： Laurent Avon , Reiner Bidenbach , Klaus Heberle
IPC分类号： H03M1/12
CPC分类号： H03M1/86
摘要： A digital-to-analog converter circuit layout includes a ratiometric digital-to-analog converter. The ratiometric digital-to-analog converter includes a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module. The a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module is configured in a controllable manner for converting digital data received at the input to a converter output voltage at the output using a reference voltage, an adjustable current as a reference current, and an adjustable impedance value. The circuit layout is characterized in that the voltage controlled oscillator includes circuit components which multiply the reference voltage by a quotient between the adjustable impedance value and the adjustable current, and which apply the multiplication results to the pulse width modulation module.
摘要翻译：数模转换器电路布局包括比例数字 - 模拟转换器。比例数字模拟转换器包括数字数据输入，转换器电压输出，压控振荡器和脉冲宽度调制模块。以可控的方式配置数字数据输入，转换器电压输出，压控振荡器和脉冲宽度调制模块，用于将在输入处接收的数字数据转换为输出处的转换器输出电压，使用参考电压，可调电流作为参考电流，并具有可调阻抗值。电路布局的特征在于，压控振荡器包括将参考电压乘以可调阻抗值和可调电流之间的商的电路组件，并将乘法结果应用于脉宽调制模块。

3. 发明申请

US20090267820A1 ANALOG/DIGITAL, CONVERSION CIRCUIT, TIMING SIGNAL GENERATION CIRCUIT, AND CONTROL DEVICE 失效
标题翻译：模拟/数字，转换电路，时序信号发生电路和控制装置
公开(公告)号：US20090267820A1
公开(公告)日：2009-10-29
申请号：US12444126
申请日：2007-08-22
申请人： Fujio Kurokawa
发明人： Fujio Kurokawa
IPC分类号： H03M1/60
CPC分类号： H03M1/207 , H03M1/60 , H03M1/661 , H03M1/86
摘要： There are provided an analog-digital converter circuit capable of performing the same degree of operation as being performed at a high-frequency oscillation pulse using a low-frequency oscillation pulse without using the high-frequency oscillation pulse, a timing signal generating circuit generating a timing signal at the high frequency, and a control device using the circuits. In an analog-digital converter circuit, a periodic signal generating circuit allows the first to j-th pulse counting devices of the N pulse counting devices to count a count value X and allows the other pulse counting devices to count a count value X−1 in each sampling period by sequentially generating N serial periodic signals at a delay time interval of [approximate value of one period (T) of periodic signals]÷N. A digital signal generating circuit converts the analog signal to the digital signal.
摘要翻译：提供了一种模数转换器电路，其能够执行与在不使用高频振荡脉冲的情况下使用低频振荡脉冲在高频振荡脉冲下执行的相同操作的程度，定时信号产生电路产生高频定时信号，以及使用该电路的控制装置。在模拟数字转换器电路中，周期信号发生电路允许N个脉冲计数装置的第一至第j个脉冲计数装置对计数值X进行计数，并允许其它脉冲计数装置对计数值X-1进行计数在每个采样周期中通过以[周期信号]的一个周期（T）的近似值] / N的延迟时间间隔依次产生N个串行周期信号。数字信号发生电路将模拟信号转换成数字信号。

4. 发明授权

US4400692A Method for periodic digital to analog conversion 失效
标题翻译：周期性数模转换的方法
公开(公告)号：US4400692A
公开(公告)日：1983-08-23
申请号：US320675
申请日：1981-11-12
申请人： Reto Klein
发明人： Reto Klein
IPC分类号： H03M1/00 , H03K13/02
CPC分类号： H03M1/82 , H03M1/86
摘要： For converting a digital value into an analog value, the digital value is first converted into a binary number and then selected auxiliary pulse trains corresponding to the binary number are used to control a switch which connects a capacitor alternatively to a reference voltage source or to ground to charge the capacitor to a voltage which corresponds to the converted analog value. The pulses in the auxiliary pulse trains associated with each binary position are grouped into pulse groups and the pulse groups of each pulse train are distributed over the duration of a conversion period in such a manner that during the superimposition of auxiliary pulse trains the number of pulse groups is not increased but the existing pulse groups are widened by being placed next to each other. In addition, the width of the single pulses forming the pulse groups is doubled so that the pulse groups are transformed into width-modulated pulses.
摘要翻译：为了将数字值转换为模拟值，首先将数字值转换为二进制数，然后使用与二进制数相对应的选定辅助脉冲串来控制将电容器与参考电压源或地之间连接的开关以将电容器充电到对应于转换的模拟值的电压。与每个二进制位置相关联的辅助脉冲串中的脉冲被分组成脉冲组，并且每个脉冲序列的脉冲组在转换周期的持续时间内分布，使得在辅助脉冲序列叠加脉冲数组不增加，但是现有的脉冲组被放置在彼此相邻的位置。此外，形成脉冲组的单个脉冲的宽度被加倍，使得脉冲组被转换成宽度调制的脉冲。

5. 发明授权

US4172384A Temperature measuring apparatus 失效
标题翻译：温度测量仪
公开(公告)号：US4172384A
公开(公告)日：1979-10-30
申请号：US909303
申请日：1978-05-24
申请人： Hiroshi Tamura , Masao Kato , Yukuya Tokumaru , Masanori Nakai
发明人： Hiroshi Tamura , Masao Kato , Yukuya Tokumaru , Masanori Nakai
IPC分类号： H03K3/282 , G01D5/248 , G01K7/24 , G01R17/00 , H03K3/02 , H03K3/03 , H03K5/15 , H03M1/00
CPC分类号： G01D5/248 , G01K7/245 , G01R17/00 , H03K3/03 , H03M1/86
摘要： A measuring apparatus comprises: a first series circuit having first and second resistors connected between a power source terminal and ground; a second series circuit having a thermistor and a third resistor connected between the power source and ground; a first variable frequency oscillator for generating a pulse signal with the frequency corresponding to the current derived from the junction between the first and second resistors of the first series circuit; a second variable frequency oscillator for generating a pulse signal with the frequency corresponding to the current derived from the junction between the thermistor and the third resistor; a first counter which counts the pulse signal from the second variable frequency oscillator to produce a high level signal till it counts a given number of pulses; and AND gate connected to the output terminal of the first variable frequency oscillator and the first counter, a second counter for counting the pulse fed from the first variable frequency oscillator via the AND gate; and a display circuit for displaying the contents of the counter. The first and second variable oscillating circuits each have an odd number of inverters which are cascade-connected and each formed of an integrated injection logic circuit with a power receiving terminal connected to the first or second series circuit, the output terminal of the last stage inverter being connected to the input terminal of the first stage inverter.
摘要翻译：一种测量装置包括：第一串联电路，其具有连接在电源端子和地之间的第一和第二电阻器; 第二串联电路，具有连接在电源和地之间的热敏电阻和第三电阻; 第一可变频率振荡器，用于产生具有与从第一串联电路的第一和第二电阻器之间的结点导出的电流的频率的脉冲信号; 第二可变频率振荡器，用于产生具有与从热敏电阻和第三电阻器之间的结点导出的电流相对应的频率的脉冲信号; 计数来自第二可变频率振荡器的脉冲信号以产生高电平信号的第一计数器，直到它计数给定数量的脉冲; 和与门连接到第一可变频率振荡器的输出端和第一计数器，第二计数器，用于通过与门对从第一可变频率振荡器馈送的脉冲进行计数; 以及显示计数器的内容的显示电路。第一和第二可变振荡电路各自具有串联连接的奇数个反相器，并且每个都由具有连接到第一或第二串联电路的电力接收端子的集成注入逻辑电路，最后一级反相器的输出端子连接到第一级逆变器的输入端子。

6. 发明授权

US3603773A Digital pulse rate generator 失效
标题翻译：数字脉冲发生器
公开(公告)号：US3603773A
公开(公告)日：1971-09-07
申请号：US3603773D
申请日：1969-08-28
申请人： VERNITRON CORP
发明人： CARISTEIN JOSEPH
IPC分类号： G06F7/68 , H03M1/00 , G06F5/06 , H03K13/256
CPC分类号： G06F7/68 , H03M1/86
摘要： In a variable pulse rate generator, a digital number is applied as parallel bits to a first bit register which stores and then transfers the bits to a bit adder under control of a clocked logic circuit. The bit adder applies its parallel bit output to a second bit register which feeds the bits back to the adder for accumulation. Periodically the adder applies a most significant bit to a pulse shaper thus creating a variable frequency output proportional to the value of the original digital number.

7. 发明授权

US2907021A Digital-to-analogue converter 失效
公开(公告)号：US2907021A
公开(公告)日：1959-09-29
申请号：US63195756
申请日：1956-12-31
申请人： RCA CORP
发明人： WOODS WILLIAM E
IPC分类号： H03M1/00
CPC分类号： H03M1/86

8. 发明授权

US11736961B2 Multi-band remote unit in a wireless communications system (WCS) 有权
公开(公告)号：US11736961B2
公开(公告)日：2023-08-22
申请号：US17837092
申请日：2022-06-10
申请人： Corning Research & Development Corporation
发明人： Yona Henia , Roi Yosy Ziv
IPC分类号： H04W24/02 , H03M1/60 , H04W72/00 , H04W72/0453 , H04W88/08 , H03M1/86 , H04W72/21 , H04W72/23 , H04W72/29
CPC分类号： H04W24/02 , H03M1/60 , H03M1/86 , H04W72/0453 , H04W72/21 , H04W72/23 , H04W72/29 , H04W88/085
摘要： A multi-band remote unit is disclosed. The multi-band remote unit includes a number of radio frequency (RF) front-end circuits configured to generate a number of downlink RF communications signals associated with a number of frequency bands based on a number of downlink digital communications signals, respectively. The multi-band remote unit also includes a digital interface circuit and a digital processing circuit. The digital interface circuit is configured to receive an encapsulated downlink digital communications signal and generate the downlink digital communications signals associated with the frequency bands based on the encapsulated downlink digital communications signal. The digital processing circuit is configured to digitally process the downlink digital communications signals before providing the downlink digital communications signals to the RF front-end circuits. As such, it may be possible to share the digital processing circuit among RF front-end circuits, thus helping to reduce cost and/or power consumption of the multi-band remote unit.

9. 发明申请

US20040207574A1 Driving circuit for vacuum fluorescent display 有权
标题翻译：真空荧光显示驱动电路
公开(公告)号：US20040207574A1
公开(公告)日：2004-10-21
申请号：US10808586
申请日：2004-03-25
发明人： Hiroyuki Arai , Syuji Motegi , Takeshi Kimura , Tetsuya Tokunaga
IPC分类号： G09G003/22
CPC分类号： H03M1/005 , G09G3/2007 , G09G3/2014 , G09G3/2077 , G09G3/22 , G09G2310/027 , H03M1/822 , H03M1/86
摘要： A driving circuit for a vacuum fluorescent display having a filament, a grid electrode and a segment electrode, the driving circuit comprising a filament driving unit for driving the filament; a grid driving unit for pulse-driving the grid electrode; and a segment driving unit for pulse-driving the segment electrode, wherein the driving circuit comprises a controlling unit for validating or invalidating the output of the filament driving unit at a proper timing.
摘要翻译：一种用于真空荧光显示器的驱动电路，其具有灯丝，栅电极和段电极，所述驱动电路包括用于驱动灯丝的灯丝驱动单元; 栅格驱动单元，用于脉冲驱动栅电极; 以及用于脉冲驱动所述分段电极的分段驱动单元，其中所述驱动电路包括用于在适当的时刻验证或使所述灯丝驱动单元的输出无效的控制单元。

10. 发明授权

US4940979A Combined rate/width modulation arrangement 失效
标题翻译：组合速率/宽度调制方案
公开(公告)号：US4940979A
公开(公告)日：1990-07-10
申请号：US186430
申请日：1988-04-26
申请人： Thomas K. Bohley , Grosvenor H. Garnett , Christopher Koerner , Charles E. Moore
发明人： Thomas K. Bohley , Grosvenor H. Garnett , Christopher Koerner , Charles E. Moore
IPC分类号： H03M1/82 , H03M1/00
CPC分类号： H03M1/68 , H03M1/822 , H03M1/86
摘要： Pulse modulation circuitry which receives n binary data bits and generates a rate/width pulse modulated signal representing the binary value of the received data bits. The lower order m of the n bits generate a rate modulated signal having a number of pulses equal to the binary value of the m bits. The remainder of the n bits width modulate the rate modulated pulses. Each least significant bit increase in the binary value of the received date bits increases the width of a rate modulated pulse by a predetermined amount.

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