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1. 发明授权

US09124287B1 Scrambler with built in test capabilities for unary DAC 有权
标题翻译：具有一体化DAC的内置测试功能的加扰器
公开(公告)号：US09124287B1
公开(公告)日：2015-09-01
申请号：US14580099
申请日：2014-12-22
申请人： PMC-SIERRA US, INC.
发明人： Stanley Ho , William Michael Lye
IPC分类号： H03M1/10 , H03M1/66 , G01R31/3167 , H03M1/06 , H03M7/02
CPC分类号： G01R31/3167 , H03M1/0673 , H03M1/109 , H03M1/66 , H03M7/02 , H03M7/165 , H03M7/22
摘要： An apparatus comprising a scrambler having a plurality of scrambler inputs and 2N scrambler outputs, and a unary-weighted digital to analog converter (DAC) connected to scrambler to generate an analog output signal based on the 2N scrambler outputs. The scrambler has N unique scrambling stages arranged in order between the scrambler inputs and the scrambler outputs from a first scrambling stage to a last scrambling stage. Each of the N unique scrambling stages has a plurality of stage inputs and outputs, with the stage inputs of the first scrambling stage connected to the scrambler inputs, the stage outputs of each scrambling stage except the last scrambling stage connected to the stage inputs of a next scrambling stage, and the stage outputs of the last scrambling stage connected to the scrambler outputs. Each of the N unique scrambling stages is operable to pass signals at the inputs to the outputs in either an unscrambled or scrambled state under control of a control bit provided by an N-bit entropy signal. When an N+1 bit input signal is applied to the scrambler inputs and the N-bit entropy signal is randomized the analog output signal from the DAC has improved linearity compared to the analog output signal generated from a non-scrambled input, and when a test input signal is applied to the scrambler inputs and the entropy signal is swept through 2N orthogonal values the analog output signal from the DAC indicates whether a fault exists in one of the scrambler and the DAC.
摘要翻译：一种包括具有多个加扰器输入和2N个加扰器输出的加扰器的装置，以及连接到加扰器的一次加密数模转换器（DAC），以基于2N个加扰器输出产生模拟输出信号。加扰器具有N个唯一的加扰阶段，其按扰频器输入和从第一加扰阶段到最后加扰阶段的加扰器输出之间的顺序排列。 N个唯一加扰阶段中的每一个具有多个级输入和输出，其中第一加扰级的级输入连接到加扰器输入，除了与第一加扰级相连的第一加扰级之外的每个加扰级的级输出下一个加扰阶段，以及连接到加扰器输出的最后一个加扰级的级输出。 N个唯一加扰级中的每一个可操作以在由N位熵信号提供的控制位的控制下以未加扰或加扰状态将输入处的信号传递到输出。当将N + 1位输入信号施加到扰频器输入并且N位熵信号被随机化时，与从非加扰输入产生的模拟输出信号相比，来自DAC的模拟输出信号具有改善的线性度，并且当测试输入信号被施加到加扰器输入，并且熵信号通过2N个正交值扫描，来自DAC的模拟输出信号指示在扰频器和DAC之一中是否存在故障。

2. 发明授权

US08988255B2 Apparatus and method for coding data based on phasor disparity 有权
标题翻译：基于相量差异编码数据的装置和方法
公开(公告)号：US08988255B2
公开(公告)日：2015-03-24
申请号：US14006702
申请日：2011-10-01
申请人： Dawson W. Kesling , Maynard C. Falconer , Kevin P. Slattery , Harry G. Skinner
发明人： Dawson W. Kesling , Maynard C. Falconer , Kevin P. Slattery , Harry G. Skinner
IPC分类号： H03M7/00 , H03M7/02 , H04L27/34
CPC分类号： H03M7/02 , H04L27/3411
摘要： A method for managing information includes receiving bits of data, determining phasors for bits at only one frequency of a transmission spectrum, combining the phasors of bits that form a phasor having a spectral energy that lies within a predetermined range, and forming a codeword from the bits of the combined phasors.
摘要翻译：一种用于管理信息的方法包括接收数据位，仅在传输频谱的一个频率处确定位的相量，组合具有处于预定范围内的频谱能量的相量的位的相量，以及从组合相量的位。

3. 发明授权

US08719322B2 Floating point format converter 有权
标题翻译：浮点格式转换器
公开(公告)号：US08719322B2
公开(公告)日：2014-05-06
申请号：US13080883
申请日：2011-04-06
申请人： David W. Bishop
发明人： David W. Bishop
IPC分类号： G06F7/00
CPC分类号： H03M7/02
摘要： A computer program product for converting from a first floating point format to a second floating point format, each floating point format having an associated base value and being represented by a significand value and a exponent value, comprising an executable algorithm to perform the steps of: determining the second exponent value by multiplying the first exponent value by a predefined constant and taking the integer portion of the result, the predefined constant being substantially equivalent to the logarithm of the first base value divided by the logarithm of the second base value; determining a bias value substantially equivalent to the second base value raised to the second exponent value divided by the first base value raised to the first exponent value; and determining the second significand value by multiplying the first significand value by the bias value.
摘要翻译：一种用于从第一浮点格式转换为第二浮点格式的计算机程序产品，每个浮点格式具有相关联的基本值并由有效值和指数值表示，包括执行以下步骤的可执行算法：通过将第一指数值乘以预定常数并获取结果的整数部分来确定第二指数值，预定义常数基本上等于第一基值除以第二基值的对数的对数; 确定基本上等于提升到所述第二指数值的所述第二基值除以被提升到所述第一指数值的所述第一基值的偏置值; 以及通过将第一有效值乘以偏置值来确定第二有效数值。

4. 发明申请

US20140028479A1 DATA TRANSLATION SYSTEM AND METHOD 有权
标题翻译：数据翻译系统和方法
公开(公告)号：US20140028479A1
公开(公告)日：2014-01-30
申请号：US13944819
申请日：2013-07-17
申请人： Raytheon Company
发明人： Frank N.G. Cheung
IPC分类号： H03M7/30
CPC分类号： H03M7/30 , H03M7/02
摘要： A data translation system and method. This invention provides a reverse approach to implement a M bit input to N bit output cumulative/monotonic transfer function, (where M>N) by a (2**N)×M bit memory instead of the conventional (2**M)×N bit memory. The invention offers substantial circuit size savings without compromising on transfer function resolution and is independent of transfer function mapping algorithms. The M bit memory content of the reverse LUT contains input video group information for each output level and the (2**N) addresses of the reverse LUT represent the corresponding transfer function output levels. This data to address representation of the input to output relationship is exactly opposite to the conventional address to data format. Search and compare methods are employed to locate the input video group that the incoming video belongs to and the associated address of the reverse LUT represents the output.
摘要翻译：数据翻译系统和方法。本发明提供了通过（2 ** N）×M位存储器而不是常规（2 ** M）位实现对N位输出累积/单调传递函数（其中M> N）的M位输入的反向方法， ×N位存储器。本发明提供了大量的电路大小节省，而不会影响传递函数分辨率，并且独立于传递函数映射算法。反向LUT的M位存储器内容包含用于每个输出电平的输入视频组信息，并且反向LUT的（2 ** N）个地址表示相应的传递函数输出电平。该数据以输入到输出关系的表示与传统的数据格式地址完全相反。采用搜索和比较方法来定位输入视频所属的输入视频组，反向LUT的相关地址表示输出。

5. 发明授权

US08509554B2 Systems and methods for optimizing bit utilization in data encoding 有权
标题翻译：用于优化数据编码中的位利用率的系统和方法
公开(公告)号：US08509554B2
公开(公告)日：2013-08-13
申请号：US13155049
申请日：2011-06-07
申请人： Stephen C. Palmer , Richard Wyatt
发明人： Stephen C. Palmer , Richard Wyatt
IPC分类号： G06K9/36
CPC分类号： H03M7/30 , H03M7/02
摘要： In one of many possible embodiments, a system for optimizing bit utilization in data encoding is provided. The exemplary system includes a data processing subsystem configured to identify a total number of unique characters within a set of data, which number represents an original base of representation of the set of data. The data processing subsystem is further configured to convert the set of data to a base of representation that is higher than the original base of representation and then encode the base-converted data with a fixed-length encoding scheme.
摘要翻译：在许多可能的实施例之一中，提供了一种用于优化数据编码中的比特利用率的系统。该示例性系统包括被配置为识别一组数据内的唯一字符的总数的数据处理子系统，该数字代表该组数据的原始表示形式。数据处理子系统还被配置为将该组数据转换为高于原始表示基数的表示基，然后用固定长度编码方案对基本转换的数据进行编码。

6. 发明授权

US08495335B2 Data translation system and method 有权
标题翻译：数据翻译系统和方法
公开(公告)号：US08495335B2
公开(公告)日：2013-07-23
申请号：US11454689
申请日：2006-06-16
申请人： Frank N. G. Cheung
发明人： Frank N. G. Cheung
IPC分类号： G06F9/26
CPC分类号： H03M7/30 , H03M7/02
摘要： A data translation system and method. This invention provides a reverse approach to implement a M bit input to N bit output cumulative/monotonic transfer function (where M>N) by a (2**N)×M bit memory instead of the conventional (2**M)×N bit memory. The invention offers substantial circuit size savings without compromising on transfer function resolution and is independent of transfer function mapping algorithms. The M bit memory content of the reverse LUT contains input video group information for each output level and the (2**N) addresses of the reverse LUT represent the corresponding transfer function output levels. This data to address representation of the input to output relationship is exactly opposite to the conventional address to data format. Search and compare methods are employed to locate the input video group that the incoming video belongs to and the associated address of the reverse LUT represents the output.
摘要翻译：数据翻译系统和方法。本发明提供了一种通过（2 ** N）×M位存储器而不是传统的（2 ** M）×M存储器实现对N位输出累积/单调传递函数（其中M> N）的M位输入的反向方法 N位存储器本发明提供了大量的电路大小节省，而不会影响传递函数分辨率，并且独立于传递函数映射算法。反向LUT的M位存储器内容包含用于每个输出电平的输入视频组信息，并且反向LUT的（2 ** N）个地址表示相应的传递函数输出电平。该数据以输入到输出关系的表示与传统的数据格式地址完全相反。采用搜索和比较方法来定位输入视频所属的输入视频组，反向LUT的相关地址表示输出。

7. 发明授权

US07791511B1 Constant weight coding of signals based on conjugate dissections 有权
标题翻译：基于共轭解剖的信号的恒权重编码
公开(公告)号：US07791511B1
公开(公告)日：2010-09-07
申请号：US11881653
申请日：2007-07-27
申请人： Neil James Alexander Sloane , Vinay Anant Vaishampayan
发明人： Neil James Alexander Sloane , Vinay Anant Vaishampayan
IPC分类号： H03M7/00
CPC分类号： H03M7/02
摘要： A method for encoding and decoding codes of constant weight that is based on conjugate dissections, which progressively modifies element values of an input vector to satisfy the constraint that each encoded symbol is to comprise integer component elements even when the encoded symbol is generated through processing that involved permuting.
摘要翻译：一种用于编码和解码恒定权重的方法，其基于共轭解析，其逐渐地修改输入向量的元素值以满足每个编码符号包含整数分量元素的约束，即使当通过处理生成编码符号时，涉及排列

8. 发明授权

US07602316B2 Data coding/decoding for electrical computers and digital data processing systems 有权
标题翻译：电子计算机和数字数据处理系统的数据编码/解码
公开(公告)号：US07602316B2
公开(公告)日：2009-10-13
申请号：US11776786
申请日：2007-07-12
申请人： Donald M. Monro
发明人： Donald M. Monro
IPC分类号： H03M7/00
CPC分类号： H03M7/02
摘要： Embodiments of methods, systems and/or devices for data coding are disclosed. Briefly, in accordance with one embodiment, data is coded and transmitted via an input/output portion of a computing platform to one or more other portions of the computing platform. An interconnect is employed to facilitate transmitting the coded data.
摘要翻译：公开了用于数据编码的方法，系统和/或设备的实施例。简而言之，根据一个实施例，将数据编码并经由计算平台的输入/输出部分传送到计算平台的一个或多个其它部分。采用互连来促进传输编码数据。

9. 发明申请

US20090115647A1 MODULATION CODING AND DECODING 有权
标题翻译：调制编码和解码
公开(公告)号：US20090115647A1
公开(公告)日：2009-05-07
申请号：US12262297
申请日：2008-10-31
申请人： Thomas Mittelholzer
发明人： Thomas Mittelholzer
IPC分类号： H03M7/14
CPC分类号： H03M5/145 , H03M7/02 , H03M7/3088
摘要： Methods and apparatus are provided for modulation coding a stream of binary input data. A 4-ary enumerative encoding algorithm is applied to the input bit-stream to produce a succession of 4-ary output symbols. The 4-ary algorithm is operative to simultaneously encode respective generalized Fibonacci codes in the odd and even interleaves of the input bit-stream. The bits of each successive 4-ary output symbol are then interleaved, producing an output bit-stream which has global and interleaved run-length constraints. Inverting the bits of the 4-ary output symbols produces an output bit-stream with (G, I)-constraints as in the PRML (G, I) codes used in reverse-concatenation modulation systems. Corresponding decoding systems are also provided.
摘要翻译：提供了用于对二进制输入数据流进行调制编码的方法和装置。 4进制枚举编码算法被应用于输入比特流以产生一系列4进制输出符号。 4进制算法可用于在输入比特流的奇数和偶数交织中同时编码相应的广义斐波纳契码。然后每个连续的4进制输出符号的比特被交织，产生具有全局和交织的游程长度约束的输出比特流。反转四元输出符号的位产生与（G，I）约束的输出比特流，如反向级联调制系统中使用的PRML（G，I）码一样。还提供了相应的解码系统。

10. 发明申请

US20090019069A1 DATA CODING/DECODING FOR ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS 有权
标题翻译：电子计算机和数字数据处理系统的数据编码/解码
公开(公告)号：US20090019069A1
公开(公告)日：2009-01-15
申请号：US11776786
申请日：2007-07-12
申请人： Donald Martin Monro
发明人： Donald Martin Monro
IPC分类号： G06F7/06 , G06F17/30
CPC分类号： H03M7/02
摘要： Embodiments of methods, systems and/or devices for data coding are disclosed. Briefly, in accordance with one embodiment, data is coded and transmitted via an input/output portion of a computing platform to one or more other portions of the computing platform. An interconnect is employed to facilitate transmitting the coded data.
摘要翻译：公开了用于数据编码的方法，系统和/或设备的实施例。简而言之，根据一个实施例，将数据编码并经由计算平台的输入/输出部分传送到计算平台的一个或多个其它部分。采用互连来促进传输编码数据。

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