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1. 发明授权

US09674084B2 Packet processing apparatus using packet processing units located at parallel packet flow paths and with different programmability 有权
公开(公告)号：US09674084B2
公开(公告)日：2017-06-06
申请号：US14462575
申请日：2014-08-19
申请人： MEDIATEK INC.
发明人： Kuo-Cheng Lu , Chang-Due Young
IPC分类号： H04L12/851 , H04L12/861 , H04L12/863 , H04L12/933 , H04L12/935 , H04L12/773
CPC分类号： H04L45/60 , H04L47/2441 , H04L47/62 , H04L49/1523 , H04L49/153 , H04L49/1538 , H04L49/1546 , H04L49/30 , H04L49/9057
摘要： A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, and a traffic manager. The ingress packet processing circuit processes ingress packets received from ingress ports. The egress packet processing circuit processes egress packets to be forwarded through egress ports. The traffic manager deals with at least packet queuing and scheduling. At least one of the ingress packet processing circuit and the egress packet processing circuit includes a first packet processing unit located at a first packet flow path, and a second packet processing unit located at a second packet flow path. The first packet flow path is parallel with the second packet flow path, and programmability of the first packet processing unit is higher than programmability of the second packet processing unit.

2. 发明授权

US08614942B2 Packet switching system and method 有权
标题翻译：分组交换系统和方法
公开(公告)号：US08614942B2
公开(公告)日：2013-12-24
申请号：US12794265
申请日：2010-06-04
申请人： Masahiko Honda
发明人： Masahiko Honda
IPC分类号： G01R31/08 , H04L12/50 , H04L12/28
CPC分类号： H04L49/153 , H04L49/206 , H04L49/255 , H04L49/3027 , H04L49/552 , H04L2012/5627 , H04L2012/565 , H04L2012/5651 , H04L2012/5681
摘要： A packet switching system capable of ensuring the sequence and continuity of packets and further compensating for delays in transmission is disclosed. Each of two redundant switch sections has a high-priority queue and a low-priority queue for each of output ports. A high-priority output selector selects one of two high-priority queues corresponding to respective ones of the two switch sections to store an output of the selected one into a high-priority output queue. A low-priority output selector selects one of two low-priority queues corresponding to respective ones of the two switch sections to store an output of the selected one into a low-priority output queue. The high-priority and low-priority output selectors are controlled depending on a system switching signal and a packet storing status of each of the high-priority and low-priority queues.
摘要翻译：公开了能够确保分组的序列和连续性并进一步补偿传输延迟的分组交换系统。两个冗余交换机部分中的每一个具有用于每个输出端口的高优先级队列和低优先级队列。高优先级输出选择器选择与两个切换部分中相应的两个切换部分相对应的两个高优先级队列中的一个，以将所选择的一个输出存储到高优先级输出队列中。低优先级输出选择器选择与两个切换部分中相应的两个切换部分相对应的两个低优先级队列之一，以将所选择的一个输出存储到低优先级输出队列中。高优先级和低优先级输出选择器根据系统切换信号和每个高优先级和低优先级队列的数据包存储状态进行控制。

3. 发明授权

US08547335B2 RFID-based input device 失效
标题翻译：基于RFID的输入设备
公开(公告)号：US08547335B2
公开(公告)日：2013-10-01
申请号：US12847087
申请日：2010-07-30
申请人： Guy M. Cohen
发明人： Guy M. Cohen
IPC分类号： G09G5/08 , G06F3/033
CPC分类号： G06F3/0346 , G06F3/03543 , G06F3/0395 , H04L49/153 , H04L49/254 , H04L49/3009 , H04L49/3072 , H04L49/3081 , H04L49/45
摘要： A device for use with a computer system includes: an array of antennas for transmitting and receiving radio frequency signals; a portable unit operating within radio frequency range of the array of antennas, wherein a location of the portable unit is estimated by the radio frequency signals transmitted from the portable unit to a processor device. The device also includes storage for storing user identification.
摘要翻译：一种与计算机系统一起使用的装置包括：用于发射和接收射频信号的天线阵列; 在天线阵列的无线电频率范围内工作的便携式装置，其中通过从便携式装置发射到处理器装置的射频信号来估计便携式装置的位置。该设备还包括用于存储用户标识的存储。

4. 发明授权

US08009702B2 Method and arrangement for local sychronization in master-slave distributed communication systems 有权
标题翻译：主从分布式通信系统中本地同步的方法和布置
公开(公告)号：US08009702B2
公开(公告)日：2011-08-30
申请号：US12777439
申请日：2010-05-11
申请人： Michel Colmant , Alan Benner , Francois G. Abel , Michel Poret , Norbert Schumacher , Alain Blanc , Mark Verhappen , Mitch Gusat
发明人： Michel Colmant , Alan Benner , Francois G. Abel , Michel Poret , Norbert Schumacher , Alain Blanc , Mark Verhappen , Mitch Gusat
IPC分类号： H04J3/06
CPC分类号： H04L49/153 , H04L49/254 , H04L49/3009 , H04L49/3072 , H04L49/3081 , H04L49/45
摘要： A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.
摘要翻译：一种通信系统，由多个模块组成，在分组的分段上并行运行，以提高速度和处理能力。一个模块作为主机，其他模块由主模块导出的控制信号控制的从模块。重要的是，在每个模块中，数据段和每个分组的相应控制信号被正确同步，因为在大系统中，承载分组段和控制信号路径的数据路径可能具有显着不同的延迟。本发明提供了传播延迟差的测量和用于在每个从模块中引入受控延迟，使得数据段和控制信号可以通过延迟其中一个或另一个来正确地相关。同步数据包除正常数据包之外传输，用于获取用于确定延迟差的时间戳。

5. 发明授权

US07633861B2 Fabric access integrated circuit configured to bound cell reorder depth 有权
标题翻译：结构访问集成电路配置为绑定单元重排序深度
公开(公告)号：US07633861B2
公开(公告)日：2009-12-15
申请号：US10831699
申请日：2004-04-23
申请人： Nelson Willhite , Mike Noll , Robert Steven Martin , Akhil Duggal , Craig Lindberg , Thomas Carleton Jones , Srinivas Komidi
发明人： Nelson Willhite , Mike Noll , Robert Steven Martin , Akhil Duggal , Craig Lindberg , Thomas Carleton Jones , Srinivas Komidi
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00
CPC分类号： H04L47/26 , H04L12/5601 , H04L45/00 , H04L45/24 , H04L45/28 , H04L47/10 , H04L47/125 , H04L47/18 , H04L47/30 , H04L47/50 , H04L49/104 , H04L49/1523 , H04L49/153 , H04L49/506 , H04L2012/5627 , H04L2012/5682
摘要： Bounding cell reorder depth is disclosed. It is determined whether a reorder buffer that is associated with a switch fabric exceeds a depth limit. In the event that the reorder buffer exceeds the depth limit, backpressure with respect to a source associated with the reorder buffer is sent. In such cases source based back pressure information is included in a reserved field in a cell that is being sent into the switch fabric. In the event that the reorder buffer does not exceed the depth limit, the cell is sent to the switch fabric. In such cases the reserved field is present in the cell but is unused.
摘要翻译：公开了边界单元重排深度。确定与交换结构相关联的重排序缓冲区是否超过深度限制。在重排序缓冲区超过深度限制的情况下，发送与重排序缓冲器相关联的源的背压。在这种情况下，基于源的背压信息被包括在被发送到交换结构中的小区中的保留字段中。在重新排序缓冲区不超过深度限制的情况下，单元被发送到交换结构。在这种情况下，保留字段存在于单元格中，但未被使用。

6. 发明授权

US07596139B2 Backplane interface adapter with error control and redundant fabric 有权
标题翻译：具有错误控制和冗余结构的背板接口适配器
公开(公告)号：US07596139B2
公开(公告)日：2009-09-29
申请号：US09988066
申请日：2001-11-16
申请人： Ronak Patel , Ming G. Wong , Yu-mei Lin , Andrew Chang
发明人： Ronak Patel , Ming G. Wong , Yu-mei Lin , Andrew Chang
IPC分类号： H04L12/28
CPC分类号： H04L45/74 , H04L47/50 , H04L47/6225 , H04L49/153 , H04L49/1538 , H04L49/25 , H04L49/30 , H04L49/3063 , H04L49/352 , H04L49/90 , H04L49/901
摘要： A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.
摘要翻译：具有错误控制和冗余结构的背板接口适配器，用于高性能网络交换机。错误控制可以由包括电平监视器，条带同步错误检测器，流量控制器和控制字符存在跟踪器的管理模块来提供。背板接口适配器的冗余结构收发器改进了适配器正确和一致地接收接收数据包的窄输入单元并向交换结构输出宽条带单元的能力。

7. 发明授权

US07512127B2 Backplane interface adapter 有权
标题翻译：背板接口适配器
公开(公告)号：US07512127B2
公开(公告)日：2009-03-31
申请号：US11804977
申请日：2007-05-21
申请人： Andrew Chang , Ronak Patel , Ming G. Wong
发明人： Andrew Chang , Ronak Patel , Ming G. Wong
IPC分类号： H04L12/28 , H04L12/56 , H04L12/54 , H04L1/00
CPC分类号： H04L49/25 , H04L47/50 , H04L47/6225 , H04L49/153 , H04L49/1538 , H04L49/30 , H04L49/3063 , H04L49/352 , H04L49/90 , H04L49/901 , Y10S370/907
摘要： A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information.
摘要翻译：用于网络交换机的背板接口适配器。背板接口适配器包括至少一个接收器，接收携带数据包的输入单元; 至少一个单元发生器，其生成包括来自输入单元的数据分组的编码单元; 以及至少一个将生成的小区发送到交换结构的发射机。小区包括目的地时隙标识符，其标识正在发送相应输入小区的交换结构的时隙。所生成的小区包括带内控制信息。

8. 发明申请

US20080225854A1 PACKET UNSTOPPER SYSTEM FOR A PARALLEL PACKET SWITCH 有权
标题翻译：用于并行分组开关的分组不间断系统
公开(公告)号：US20080225854A1
公开(公告)日：2008-09-18
申请号：US12126679
申请日：2008-05-23
申请人： Francois Le Maut , Rene Glaise , Michel Poret , Rene Gallezot
发明人： Francois Le Maut , Rene Glaise , Michel Poret , Rene Gallezot
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L49/153 , H04L12/5601 , H04L49/1523 , H04L49/256 , H04L49/30 , H04L49/3045 , H04L49/3081 , H04L49/50 , H04L2012/5635 , H04L2012/565 , H04L2012/5679 , H04L2012/5682
摘要： A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.
摘要翻译：用于控制出口缓冲器饱和的系统包括用于每个数据分组流的比较器，用于将临时存储在出口缓冲器内的数据分组“WPC”的数量与预定义的阈值“WPCth”进行比较。存储最后接收的顺序数据分组的分组序列号“PSNr”和通过多个切换平面中的相应的接收平面接收的每个最高分组序列号“HPSNj”。当数据包“WPC”的数量超过预定义的阈值“WPCth”时，通过将最后接收的按顺序分组序列号“PSNr”与每个最高分组序列号'HPSNj'进行比较，确定哪个交换平面在多个交换平面中，可以进行数据分组的流动。

9. 发明授权

US07236490B2 Backplane interface adapter 有权
标题翻译：背板接口适配器
公开(公告)号：US07236490B2
公开(公告)日：2007-06-26
申请号：US09855038
申请日：2001-05-15
申请人： Andrew Chang , Ronak Patel , Ming G Wong
发明人： Andrew Chang , Ronak Patel , Ming G Wong
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/25 , H04L47/50 , H04L47/6225 , H04L49/153 , H04L49/1538 , H04L49/30 , H04L49/3063 , H04L49/352 , H04L49/90 , H04L49/901 , Y10S370/907
摘要： A backplane interface adapter for a high-performance network switch. The backplane interface adapter receives narrow input cells carrying packets of data and outputs wide striped cells to a switching fabric. One traffic processing path through the backplane interface adapter includes deserializer receivers, a traffic sorter, wide cell generators, stripe send queues, a backplane transmit arbitrator, and serializer transmitters. Another traffic processing path through the backplane interface adapter includes deserialize receivers, a stripe interface, stripe receive synchronization queues, a controller, wide/narrow cell translator, destination queues, and serializer transmitters. An encoding scheme for packets of data carried in wide striped cells is provided.
摘要翻译：用于高性能网络交换机的背板接口适配器。背板接口适配器接收携带数据包的窄输入单元，并向交换结构输出宽条带单元。通过背板接口适配器的一个流量处理路径包括解串器接收器，流量分拣机，宽单元发生器，条带发送队列，背板发送仲裁器和串行器发送器。通过背板接口适配器的另一业务处理路径包括反序列化接收机，条带接口，条带接收同步队列，控制器，宽/窄小区转换器，目的地队列和串行发送器。提供了一种用于在宽条带单元格中携带的数据分组的编码方案。

10. 发明申请

US20060285488A1 PACKET SWITCHING SYSTEM AND METHOD 失效
标题翻译：分组开关系统及方法
公开(公告)号：US20060285488A1
公开(公告)日：2006-12-21
申请号：US11467478
申请日：2006-08-25
申请人： Masahiko Honda
发明人： Masahiko Honda
IPC分类号： H04J3/14 , H04L12/56
CPC分类号： H04L49/153 , H04L49/206 , H04L49/255 , H04L49/3027 , H04L49/552 , H04L2012/5627 , H04L2012/565 , H04L2012/5651 , H04L2012/5681
摘要： A packet switching system capable of ensuring the sequence and continuity of packets and further compensating for delays in transmission is disclosed. Each of two redundant switch sections has a high-priority queue and a low-priority queue for each of output ports. A high-priority output selector selects one of two high-priority queues corresponding to respective ones of the two switch sections to store an output of the selected one into a high-priority output queue. A low-priority output selector selects one of two low-priority queues corresponding to respective ones of the two switch sections to store an output of the selected one into a low-priority output queue. The high-priority and low-priority output selectors are controlled depending on a system switching signal and a packet storing status of each of the high-priority and low-priority queues.
摘要翻译：公开了能够确保分组的序列和连续性并进一步补偿传输延迟的分组交换系统。两个冗余交换机部分中的每一个具有用于每个输出端口的高优先级队列和低优先级队列。高优先级输出选择器选择与两个切换部分中相应的两个切换部分相对应的两个高优先级队列中的一个，以将所选择的一个输出存储到高优先级输出队列中。低优先级输出选择器选择与两个切换部分中相应的两个切换部分相对应的两个低优先级队列之一，以将所选择的一个输出存储到低优先级输出队列中。高优先级和低优先级输出选择器根据系统切换信号和每个高优先级和低优先级队列的数据包存储状态进行控制。

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