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1. 发明申请

US20190075662A1 SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST 审中-公开
公开(公告)号：US20190075662A1
公开(公告)日：2019-03-07
申请号：US16181180
申请日：2018-11-05
申请人： SANMINA CORPORATION
发明人： Shinichi Iketani , Dale Kersten
IPC分类号： H05K3/42 , H05K1/11 , H05K1/02
CPC分类号： H05K3/429 , H05K1/0251 , H05K1/115 , H05K2201/0187 , H05K2201/09536 , H05K2201/09645 , H05K2203/061 , H05K2203/0713 , Y10T29/49165
摘要： A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

2. 发明申请

US20180175531A1 CONNECTION STRUCTURE BETWEEN FLAT CABLE AND ELECTRONIC CIRCUIT BOARD 审中-公开
公开(公告)号：US20180175531A1
公开(公告)日：2018-06-21
申请号：US15843066
申请日：2017-12-15
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sung-soo KIM
IPC分类号： H01R12/79
CPC分类号： H01R12/79 , H01R12/7023 , H01R12/718 , H01R12/778 , H01R12/88 , H05K1/184 , H05K2201/09181 , H05K2201/09645 , H05K2201/10189 , H05K2201/10356
摘要： A connection structure between a flat cable and an electronic circuit board includes an electronic circuit board; a cable connection hole formed to penetrate the electronic circuit board; a plurality of internal contacts provided on an inner surface of the cable connection hole; and a flat cable provided with a plurality of contacts which correspond to the plurality of internal contacts of the cable connection hole and are exposed to one side surface of the flat cable. When one end of the flat cable is inserted into the cable connection hole of the electronic circuit board, the plurality of contacts of the flat cable are in contact with the plurality of internal contacts of the cable connection hole, respectively.

3. 发明申请

US20180092222A1 SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST 审中-公开
公开(公告)号：US20180092222A1
公开(公告)日：2018-03-29
申请号：US15723135
申请日：2017-10-02
申请人： SANMINA CORPORATION
发明人： Shinichi Iketani , Dale Kersten
IPC分类号： H05K3/42 , H05K1/11
CPC分类号： H05K3/429 , H05K1/0251 , H05K1/115 , H05K2201/0187 , H05K2201/09536 , H05K2201/09645 , H05K2203/061 , H05K2203/0713 , Y10T29/49165
摘要： A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

4. 发明授权

US09781844B2 Simultaneous and selective wide gap partitioning of via structures using plating resist 有权
公开(公告)号：US09781844B2
公开(公告)日：2017-10-03
申请号：US14205331
申请日：2014-03-11
申请人： SANMINA CORPORATION
发明人： Shinichi Iketani , Dale Kersten
IPC分类号： H05K3/42 , H05K1/11 , H05K1/02
CPC分类号： H05K3/429 , H05K1/0251 , H05K1/115 , H05K2201/0187 , H05K2201/09536 , H05K2201/09645 , H05K2203/061 , H05K2203/0713 , Y10T29/49165
摘要： A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

5. 发明授权

US09128679B2 Slot and memory module for a slot standing interconnect 有权
标题翻译：插槽和内存模块，用于插槽连接
公开(公告)号：US09128679B2
公开(公告)日：2015-09-08
申请号：US13600810
申请日：2012-08-31
申请人： Darryl J. McKenney , Daniel Toohey , Stephen Mariani , Michael Gust , Absu Methratta , Timothy Fleury , Steven Imperalli
发明人： Darryl J. McKenney , Daniel Toohey , Stephen Mariani , Michael Gust , Absu Methratta , Timothy Fleury , Steven Imperalli
IPC分类号： H05K1/14 , G06F1/18 , H01R12/52 , H05K3/40 , H05K1/11 , H05K3/34 , H05K3/36
CPC分类号： G06F1/185 , B23C2220/36 , H01R12/52 , H05K1/11 , H05K3/34 , H05K3/366 , H05K3/403 , H05K2201/09036 , H05K2201/09181 , H05K2201/09645 , H05K2201/10159 , H05K2203/0228 , Y10T29/49124 , Y10T29/4913 , Y10T29/49144 , Y10T409/303752
摘要： According to exemplary embodiments, a controlled-depth slot extending into a circuit board is provided. The controlled depth slot may be milled, and may comprise ½ radial plated through-holes to generate a solderable “D” interconnect feature. The slot may include interconnect features on one to five sides. According to another exemplary embodiment, a circuit board having a depth-controlled interconnect slot is provided in conjunction with one or more solderable technology modules. The one or more solderable technology modules may include memory devices, power devices such as Point of Load Supplies (POLS), security devices and anti-tamper devices, capacitance devices, and other types of chips such as Field Programmable Gate Arrays (FPGAs). The solderable technology modules may be soldered into the slot to secure the modules in the slot and connect the modules to interconnects on the circuit board.
摘要翻译：根据示例性实施例，提供延伸到电路板中的受控深度槽。受控深度槽可以被铣削，并且可以包括1/2个径向电镀通孔，以产生可焊接的“D”互连特征。插槽可以包括一至五侧的互连特征。根据另一示例性实施例，具有深度控制互连槽的电路板与一个或多个可焊接技术模块一起提供。一个或多个可焊接技术模块可以包括存储器件，诸如负载供应点（POLS），安全装置和防篡改装置，电容装置和诸如现场可编程门阵列（FPGA）的其它类型的芯片的功率器件。可焊接技术模块可以焊接到插槽中，以将模块固定在插槽中，并将模块连接到电路板上的互连。

6. 发明申请

US20150245491A1 INTEGRATED CIRCUIT STRUCTURES HAVING OFF-AXIS IN-HOLE CAPACITOR 有权
标题翻译：具有离轴孔内电容器的集成电路结构
公开(公告)号：US20150245491A1
公开(公告)日：2015-08-27
申请号：US14708755
申请日：2015-05-11
申请人： International Business Machines Corporation
发明人： Mark C. Lamorey , Janak G. Patel , Peter Slota, JR. , David B. Stone
IPC分类号： H05K1/18 , H05K1/11
CPC分类号： H05K1/183 , H05K1/0231 , H05K1/11 , H05K1/181 , H05K1/184 , H05K2201/09645 , H05K2201/10015 , H05K2201/10507 , Y02P70/611 , Y10T29/49135
摘要： Various embodiments include integrated circuit structures having an off-axis in-hole capacitor. In some embodiments, an integrated circuit (IC) structure includes: a substrate layer having an upper surface; an IC chip at least partially contained within the substrate layer and aligned with a minor axis perpendicular to the upper surface of the substrate layer; an aperture in the substrate layer, the aperture physically separated from the IC chip; and a capacitor in the aperture and at least partially contained within the substrate layer, the capacitor being physically isolated from the IC chip, wherein the capacitor is aligned with an axis perpendicular to the upper surface of the substrate layer and offset from the minor axis of the IC chip.
摘要翻译：各种实施例包括具有离轴孔内电容器的集成电路结构。在一些实施例中，集成电路（IC）结构包括：具有上表面的基底层; 至少部分地包含在所述衬底层内并与垂直于所述衬底层的上表面的短轴对准的IC芯片; 所述基板层中的孔，所述孔与所述IC芯片物理分离; 以及孔中的电容器，并且至少部分地包含在所述衬底层内，所述电容器与所述IC芯片物理隔离，其中所述电容器与垂直于所述衬底层的上表面的轴线对准，并且偏离所述衬底层的短轴 IC芯片。

7. 发明授权

US09078374B2 Screening process for manufacturing a Z-directed component for a printed circuit board 有权
标题翻译：用于制造用于印刷电路板的Z定向部件的筛选过程
公开(公告)号：US09078374B2
公开(公告)日：2015-07-07
申请号：US13222418
申请日：2011-08-31
申请人： Paul Kevin Hall , Keith Bryan Hardin , Zachary Charles Nathan Kratzer , Qing Zhang
发明人： Paul Kevin Hall , Keith Bryan Hardin , Zachary Charles Nathan Kratzer , Qing Zhang
IPC分类号： B05D5/12 , H05K3/00 , H01C17/06 , H05K1/18 , H05K3/40 , C04B35/622 , H05K1/02 , B28B7/16
CPC分类号： H05K1/184 , B28B7/16 , C04B35/622 , H05K1/0231 , H05K1/0233 , H05K1/0248 , H05K1/0251 , H05K3/4046 , H05K3/4667 , H05K2201/09645
摘要： A method for manufacturing a z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes adding a substrate material to a mold defining the shape of a layer of the z-directed component. A top surface of the substrate material in the mold is leveled. The substrate material in the mold is treated and the layer of the z-directed component is formed. A conductive material is applied to at least one surface of the formed layer. The z-directed component is formed that includes a stack of component layers that includes the formed layer.
摘要翻译：根据一个示例性实施例的用于制造用于插入到印刷电路板的安装孔中的z定向部件的方法包括将衬底材料添加到限定z定向部件的层的形状的模具中。模具中的基材材料的顶表面被平整。对模具中的基底材料进行处理，并且形成z定向部件的层。将导电材料施加到所形成的层的至少一个表面。形成z定向分量，其包括包括所形成的层的一组成分层。

8. 发明申请

US20150181724A1 METHODS OF FORMING SEGMENTED VIAS FOR PRINTED CIRCUIT BOARDS 审中-公开
标题翻译：形成印刷电路板的分离VIAS的方法
公开(公告)号：US20150181724A1
公开(公告)日：2015-06-25
申请号：US14574138
申请日：2014-12-17
申请人： Sanmina Corporation
发明人： Shinichi IKETANI , Dale KERSTEN
IPC分类号： H05K3/42 , H05K3/06
CPC分类号： H05K3/429 , H05K2201/09645 , H05K2203/0713 , Y10T29/49165
摘要： Novel methods for forming a printed circuit board (PCB) having one or more segmented vias are provided, including improved methods of removing the catalyst after the plating process when forming a segmented via in the PCB. After the electroless plating, excess catalyst on the surface of the plating resist is removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, electrolytic plating is then applied to the through holes and the outer layer circuit or signal traces are formed. That is, the etching of paths on the conductive foils/layers of the core structure.
摘要翻译：提供了用于形成具有一个或多个分段通孔的印刷电路板（PCB）的新方法，包括在电镀工艺之后形成分段通孔在PCB中去除催化剂的改进方法。在化学镀后，使用催化剂去除剂，例如至少包含亚硝酸根或亚硝酸根离子和卤素离子的酸性溶液除去电镀抗蚀剂表面上的过量催化剂，或者催化剂去除剂可以是电镀抗蚀剂的蚀刻剂，例如包括氧，氮，氩和四氟甲烷中的至少一种的碱金属高锰酸盐化合物溶液或等离子气体，或这些气体中的至少两种的混合物。除去过量的催化剂后，对通孔施加电解电镀，形成外层电路或信号迹线。也就是说，蚀刻在芯结构的导电箔/层上的路径。

9. 发明申请

US20150101858A1 CAVITIES CONTAINING MULTI-WIRING STRUCTURES AND DEVICES 有权
标题翻译：包含多层结构和设备的CAVITIES
公开(公告)号：US20150101858A1
公开(公告)日：2015-04-16
申请号：US14573461
申请日：2014-12-17
申请人： Invensas Corporation
发明人： Cyprian Emeka Uzoh , Craig Mitchell , Belgacem Haba , Ilyas Mohammed
IPC分类号： H05K1/02 , H05K1/11 , H01R12/71
CPC分类号： H05K1/0271 , H01L23/49827 , H01L2924/0002 , H01R12/714 , H05K1/114 , H05K1/115 , H05K3/42 , H05K2201/09645 , H05K2201/10378 , H05K2203/0242 , H05K2203/025 , Y10T29/49165 , H01L2924/00
摘要： A method is disclosed for making an interconnection component. The steps include forming a mask layer covering a first opening in a sheet-like element that has first and second opposed surfaces; forming a plurality of mask openings in the mask layer, wherein the first opening and a portion of the first surface are partly aligned with each mask opening; and forming electrical conductors on spaced apart portions of the first surface and on spaced apart portions of the interior surface within the first opening which are exposed by the mask openings. The element may consist essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. Each conductor may extend along an axial direction of the first opening and the first conductors may be fully separated from one another within the first opening.
摘要翻译：公开了一种制造互连部件的方法。所述步骤包括在具有第一和第二相对表面的片状元件中形成覆盖第一开口的掩模层; 在所述掩模层中形成多个掩模开口，其中所述第一开口和所述第一表面的一部分与每个掩模开口部分对准; 以及在所述第一开口中的所述第一表面的间隔开的部分和所述第一开口内的所述内表面的间隔开的部分上形成电导体，所述部分被所述掩模开口暴露。元件可以基本上由热膨胀系数小于10ppm /℃的材料组成。每个导体可以沿着第一开口的轴向方向延伸，并且第一导体可以在第一开口内彼此完全分离。

10. 发明申请

US20150026973A1 METHOD OF PRODUCING ELECTRONIC COMPONENTS 有权
标题翻译：生产电子元件的方法
公开(公告)号：US20150026973A1
公开(公告)日：2015-01-29
申请号：US14334688
申请日：2014-07-18
申请人： Murata Manufacturing Co., Ltd.
发明人： Kazuto OGAWA , Takashi WATANABE , Junya SHIMAKAWA
IPC分类号： H05K3/30
CPC分类号： H05K3/0052 , H05K1/141 , H05K3/3442 , H05K2201/049 , H05K2201/0909 , H05K2201/09181 , H05K2201/09645 , H05K2201/10636 , H05K2203/0191 , H05K2203/1563 , Y02P70/611 , Y10T29/4913
摘要： A method of producing electronic components each including a substrate-type terminal and a device connected to the substrate-type terminal is performed such that the substrate-type terminal includes a substrate body including a rectangular or substantially rectangular first principal surface extending in first and second directions perpendicular or substantially perpendicular to each other. The device is disposed on the first principal surface. The method includes supporting a substrate that is to become an assembly in which the plurality of substrate-type terminals are arranged in a matrix using a first support member, cutting the substrate supported by the first support member into the plurality of substrate-type terminals, and mounting the device on the first principal surface of the substrate body of each of the plurality of substrate-type terminals obtained by cutting.
摘要翻译：一种电子部件的制造方法，其特征在于，具有基板型端子和与所述基板型端子连接的装置的电子部件的制造方法，使得所述基板型端子包括基板主体，所述基板主体包括第一和第二延伸的长方形或大致矩形的第一主面方向彼此垂直或基本垂直。该装置设置在第一主表面上。该方法包括使用第一支撑构件支撑待成为其中多个基板型端子以矩阵状排列的组件的基板，将由第一支撑构件支撑的基板切割成多个基板型端子，以及将所述装置安装在通过切割获得的所述多个基板型端子中的每一个的所述基板主体的所述第一主表面上。

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