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1. 发明授权

US11640303B2 Calculating device 有权
公开(公告)号：US11640303B2
公开(公告)日：2023-05-02
申请号：US17027744
申请日：2020-09-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kosuke Tatsumura , Hayato Goto
IPC分类号： G06F9/38 , G06F7/72 , G06F9/30 , G06F7/57
摘要： According to one embodiment, a calculating device includes a first memory, a second memory, a third memory, a first arithmetic module, a second arithmetic module, a first conductive line electrically connecting a first output terminal of the first memory and a first input terminal of the first arithmetic module, a second conductive line electrically connecting a second output terminal of the first memory and a first input terminal of the second arithmetic module, a third conductive line electrically connecting a first output terminal of the second memory and a second input terminal of the second arithmetic module, a fourth conductive line electrically connecting a first output terminal of the third memory and a third input terminal of the second arithmetic module, and a fifth conductive line electrically connecting a first output terminal of the second arithmetic module and a second input terminal of the first arithmetic module.

2. 发明申请

US20220012306A1 INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM 有权
公开(公告)号：US20220012306A1
公开(公告)日：2022-01-13
申请号：US17486468
申请日：2021-09-27
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA DIGITAL SOLUTIONS CORPORATION
发明人： Masaru SUZUKI , Hayato Goto , Kosuke Tatsumura
IPC分类号： G06F17/16 , G06F7/58 , G06F7/492
摘要： An information processing device includes a storage unit and a processing circuit. The storage unit is configured to store a first variable and the second variable. The processing circuit is configured to update a first vector having the first variable by weighted addition of the corresponding second variable to the first variable, update a second vector having the second variable by weighting the first variable with a first coefficient that monotonically increases or monotonically decreases depending on the number of updates, adding the weighted first variable to the corresponding second variable, calculating a problem term using a plurality of the first variables, and adding the problem term to the second variable, and repeat updating of the first vector and the second vector, then initialize the second variable of the second vector using a pseudo random number, and then repeat updating of the first vector and the second vector again.

3. 发明申请

US20190266212A1 CALCULATING DEVICE, CALCULATION PROGRAM, RECORDING MEDIUM, AND CALCULATION METHOD 审中-公开
公开(公告)号：US20190266212A1
公开(公告)日：2019-08-29
申请号：US16123146
申请日：2018-09-06
申请人： Kabushiki Kaisha Toshiba
发明人： Hayato Goto , Kosuke Tatsumura
IPC分类号： G06F17/11 , G06F9/30
摘要： According to one embodiment, a calculating device includes a processor repeating a processing procedure. The processing procedure includes a first variable update and a second variable update. The first variable update includes updating an ith entry of a first variable xi by adding a first function to the ith entry of the first variable xi before the first variable update. The second variable update includes updating the ith entry of the second variable yi by adding a second function and a third function to the ith entry of the second variable yi before the second variable update. The processor performs at least an output of at least one of the ith entry of the first variable xi obtained after the repeating of the processing procedure or a function of the ith entry of the first variable xi obtained after the repeating of the processing procedure.

4. 发明授权

US09601190B2 Semiconductor integrated circuit 有权
公开(公告)号：US09601190B2
公开(公告)日：2017-03-21
申请号：US14988034
申请日：2016-01-05
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Koichiro Zaitsu , Kosuke Tatsumura , Masato Oda
IPC分类号： G11C5/06 , G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/0026 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C2013/009 , G11C2213/33 , G11C2213/34 , G11C2213/77 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A semiconductor integrated circuit according to an embodiment includes: N (≧1) input wiring lines; M (≧1) output wiring lines; N first wiring lines corresponding to the N input wiring lines; K (>M) second wiring lines crossing the N first wiring lines; a plurality of first resistive change elements disposed at intersections of the first wiring lines and the second wiring lines, each of the first resistive change elements including a first electrode connecting to a corresponding one of the first wiring lines, a second electrode connecting to a corresponding one of the second wiring lines, and a first resistive change layer disposed between the first electrode and the second electrode; a first controller controlling a voltage applied to the first wiring lines; a second controller controlling a voltage applied to the second wiring lines; and a selection circuit selecting M second wiring lines from the K second wiring lines.

5. 发明授权

US09276581B2 Nonvolatile programmable logic switch 有权
标题翻译：非易失性可编程逻辑开关
公开(公告)号：US09276581B2
公开(公告)日：2016-03-01
申请号：US14624961
申请日：2015-02-18
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Mari Matsumoto , Kosuke Tatsumura , Shinichi Yasuda , Koichiro Zaitsu
IPC分类号： H03K19/173 , H03K19/0185 , H03K19/177
CPC分类号： H03K19/1735 , H03K19/018585 , H03K19/1776
摘要： A nonvolatile programmable logic switch of an embodiment includes: a cell including: a first memory including a first terminal connected to a first wiring line, and a second terminal; a second memory including a third terminal connected to a second wiring line, and a fourth terminal connected to the second terminal of the first memory; a first transistor, of which one of a source and a drain is connected to the second and fourth terminals, the other of the source and the drain is connected to a third wiring line, and a gate is connected to a fourth wiring line; and a second transistor, of which one of a source and a drain is connected to the second and fourth terminals, the other of the source and the drain is connected to a gate of a pass transistor, and a gate is connected to a fifth wiring line.
摘要翻译：实施例的非易失性可编程逻辑开关包括：单元，包括：第一存储器，包括连接到第一布线的第一端子和第二端子; 第二存储器，包括连接到第二布线的第三端子和连接到第一存储器的第二端子的第四端子; 源极和漏极之一连接到第二和第四端子的第一晶体管，源极和漏极中的另一个连接到第三布线，栅极连接到第四布线; 以及第二晶体管，其源极和漏极中的一个连接到第二和第四端子，源极和漏极中的另一个连接到通过晶体管的栅极，栅极连接到第五布线线。

6. 发明申请

US20150262624A1 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US20150262624A1
公开(公告)日：2015-09-17
申请号：US14491074
申请日：2014-09-19
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Koichiro Zaitsu , Kosuke Tatsumura
IPC分类号： G11C5/06 , G11C17/18 , G11C17/16
CPC分类号： G11C17/18 , G11C5/063 , G11C17/146
摘要： A semiconductor nonvolatile memory device of an embodiment includes: a plurality of transistors arranged in a matrix, the transistors in the same row being connected in series to form a transistor string having a first terminal and a second terminal; a plurality of first wiring lines each corresponding to one of the columns, and being connected to the gates of the transistors of the corresponding column; a common first electrode connected to each semiconductor region in which each transistor is disposed; and a write unit that selects one of the first wiring lines and one of the transistor strings, and applies a first voltage to the first electrode, a first write voltage to the selected first wiring line, a second voltage to the other first wiring lines, and a second write voltage to the first terminal and the second terminal of the selected transistor string in a write operation.
摘要翻译：实施例的半导体非易失性存储器件包括：以矩阵形式布置的多个晶体管，同一行中的晶体管串联连接以形成具有第一端子和第二端子的晶体管串; 多个第一布线，每一个对应于一列之一，并连接到相应列的晶体管的栅极; 连接到其中设置每个晶体管的每个半导体区域的公共第一电极; 以及写入单元，其选择所述第一布线和所述晶体管串中的一个，并将第一电压施加到所述第一电极，对所选择的第一布线施加第一写入电压，向所述其它第一布线施加第二电压，以及在写入操作中第二写入电压到所选择的晶体管串的第一端子和第二端子。

7. 发明授权

US09025373B2 Non-volatile programmable switch 有权
标题翻译：非易失性可编程开关
公开(公告)号：US09025373B2
公开(公告)日：2015-05-05
申请号：US13776416
申请日：2013-02-25
申请人： Kabushiki Kaisha Toshiba
发明人： Kosuke Tatsumura , Koichiro Zaitsu , Mari Matsumoto , Shinichi Yasuda
IPC分类号： G11C11/34 , H01L27/088 , G11C11/40 , H01L21/28 , H01L27/118 , H01L27/115
CPC分类号： H01L27/088 , G11C11/40 , H01L21/28273 , H01L21/28282 , H01L27/1156 , H01L27/11803
摘要： According to one embodiment, a non-volatile programmable switch according to this embodiment includes first and second non-volatile memory transistors, and a common node that is connected to the output side terminals of the first and second non-volatile memory transistors, and a logic transistor unit that is connected to the common node. A length of a gate electrode of the first and second non-volatile memory transistors in a channel longitudinal direction is shorter than a length of the charge storage film in the channel longitudinal direction.
摘要翻译：根据一个实施例，根据本实施例的非易失性可编程开关包括第一和第二非易失性存储器晶体管，以及连接到第一和第二非易失性存储晶体管的输出侧端子的公共节点，以及连接到公共节点的逻辑晶体管单元。第一和第二非易失性存储晶体管的沟道纵向方向上的栅电极的长度短于电荷储存膜在沟道纵向方向上的长度。

8. 发明授权

US08884648B2 Programmable logic switch 有权
标题翻译：可编程逻辑开关
公开(公告)号：US08884648B2
公开(公告)日：2014-11-11
申请号：US13856448
申请日：2013-04-04
申请人： Kabushiki Kaisha Toshiba
发明人： Koichiro Zaitsu , Kosuke Tatsumura , Mari Matsumoto , Shinichi Yasuda , Masato Oda , Haruka Kusai , Kiwamu Sakuma
IPC分类号： H03K19/173 , H03K19/0185
CPC分类号： H03K19/018585 , G11C5/146 , G11C16/10 , G11C16/12 , H03K19/1737
摘要： One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.
摘要翻译：一个实施例提供一种可编程逻辑开关，其中在同一个阱中形成第一非易失性存储器和第二非易失性存储器，并且其中将第一非易失性存储器从擦除状态改变为写入状态，并使第二非易失性存储器处于擦除状态时，将第一写入电压施加到与第一和第二非易失性存储器的栅电极连接的第一线，第二写入电压被施加到连接到第一非易失性存储器中的源极的第二线，并且第三写入低于第二写入电压的电压被施加到连接到第二非易失性存储器的源极的第四线路。

9. 发明申请

US20140022840A1 NON-VOLATILE PROGRAMMABLE SWITCH 有权
标题翻译：非易失可编程开关
公开(公告)号：US20140022840A1
公开(公告)日：2014-01-23
申请号：US13776416
申请日：2013-02-25
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kosuke Tatsumura , Koichiro Zaitsu , Mari Matsumoto , Shinichi Yasuda
IPC分类号： H01L27/088 , G11C11/40
CPC分类号： H01L27/088 , G11C11/40 , H01L21/28273 , H01L21/28282 , H01L27/1156 , H01L27/11803
摘要： According to one embodiment, a non-volatile programmable switch according to this embodiment includes first and second non-volatile memory transistors, and a common node that is connected to the output side terminals of the first and second non-volatile memory transistors, and a logic transistor unit that is connected to the common node. A length of a gate electrode of the first and second non-volatile memory transistors in a channel longitudinal direction is shorter than a length of the charge storage film in the channel longitudinal direction.
摘要翻译：根据一个实施例，根据本实施例的非易失性可编程开关包括第一和第二非易失性存储器晶体管，以及连接到第一和第二非易失性存储晶体管的输出侧端子的公共节点，以及连接到公共节点的逻辑晶体管单元。第一和第二非易失性存储晶体管的沟道纵向方向上的栅电极的长度短于电荷储存膜在沟道纵向方向上的长度。

10. 发明授权

US11256779B2 Calculation apparatus, calculation method and computer program product 有权
公开(公告)号：US11256779B2
公开(公告)日：2022-02-22
申请号：US16801429
申请日：2020-02-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Taro Kanao , Kosuke Tatsumura , Hayato Goto
IPC分类号： G06F17/16
摘要： A calculation apparatus according to an embodiment includes one or more processing circuits configured to function as an interaction unit, a first addition unit, and a time evolution unit. The interaction unit generates N first intermediate variables obtained by performing a matrix computing on the N first variables and the coefficient matrix at the first time. The first addition unit calculates N second variables at the second time at which the sampling period elapses from the first time. The time evolution unit executes a time evolution process on the N second variables at the first time to generate N first variables at the second time. If the N first variables at the second time unsatisfied a predetermined constraint condition, the time evolution unit changes the N second variables at the second time in a direction of satisfying the constraint condition.

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