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    • 1. 发明授权
    • LCD driving circuitry with reduced number of control signals
    • LCD驱动电路,控制信号数量减少
    • US06831625B2
    • 2004-12-14
    • US10160173
    • 2002-06-04
    • Yasuhiro MatsushimaSunao EtohYutaka Takafuji
    • Yasuhiro MatsushimaSunao EtohYutaka Takafuji
    • G09G328
    • G09G3/3674G09G3/3677G09G3/3685G09G3/3688G09G2310/0205G09G2310/0224
    • A liquid crystal display device according to the present invention includes an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, and a vertical drive circuit for driving the active matrix array, in which the vertical drive circuit includes: scanning circuits N in number (N being a positive integer), which receive a start pulse and output pulse signals, the respective scanning circuits sequentially shifting the pulse signal by one-half of a clock signal cycle each; AND gate circuits N×M in number (M being an integer no less than 2), each provided with a first control terminal and a second control terminal, every M adjacent AND gate circuits being connected together via the first control terminals thereof, which receive a signal from one of the N scanning circuits, and every Mth AND gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal; and NAND gate circuits, each of which receives an output from one of the AND gate circuits and one of two kinds of third control signal outputted by a third control terminal.
    • 根据本发明的液晶显示装置包括由多个扫描线和多个信号线之间的交叉点处提供的开关元件和用于驱动有源矩阵阵列的垂直驱动电路构成的有源矩阵阵列, 垂直驱动电路包括:数字(N为正整数)的扫描电路N,其接收起始脉冲和输出脉冲信号,各个扫描电路将脉冲信号顺序地移位每个时钟信号周期的一半; AND门电路NxM(M为2以上的整数),各自设置有第一控制端子和第二控制端子,每M个相邻的AND门电路经由其第一控制端子连接在一起,其接收信号 从N个扫描电路中的一个和每个第M个AND门电路经由其第二控制端连接在一起,它们接收M种第二控制信号中的一种; 以及NAND门电路,每个NAND门电路接收来自与门电路之一的输出和由第三控制端输出的两种第三控制信号之一。
    • 5. 发明授权
    • Active matrix display device
    • 主动矩阵显示装置
    • US06756961B2
    • 2004-06-29
    • US10072117
    • 2002-02-08
    • Jason R. HectorNeil C. Bird
    • Jason R. HectorNeil C. Bird
    • G09G328
    • G09G3/2011G09G3/3688G09G3/3696G09G2310/027G09G2310/0297G09G2330/021
    • A display has circuitry (50) which generates all possible pixel drive signal levels on separate signal level lines. A buffer (54) is associated with each signal level line. The outputs of the buffers are selectably switchable onto the columns. The signal levels for each column are stored in a memory (72) and the buffers are controlled in dependence on the stored signal levels. The response of the buffers is heavily dependent on the output load, and there is a very large variation in the output load of the buffers (54), as a function of the number of columns to which the buffer output is to be provided. The buffers are controlled in dependence on stored signal levels to ensure stability of the buffers for any output load.
    • 显示器具有在单独的信号电平线上产生所有可能的像素驱动信号电平的电路(50)。 缓冲器(54)与每个信号电平线相关联。 缓冲器的输出可选择地切换到列上。 每列的信号电平存储在存储器(72)中,并且根据所存储的信号电平来控制缓冲器。 缓冲器的响应在很大程度上取决于输出负载,并且缓冲器(54)的输出负载存在非常大的变化,作为要提供缓冲器输出的列数的函数。 缓冲器根据存储的信号电平进行控制,以确保缓冲器对于任何输出负载的稳定性。
    • 10. 发明授权
    • Method of driving AC surface-discharge type plasma display panel
    • 交流表面放电型等离子体显示面板的驱动方法
    • US06720941B2
    • 2004-04-13
    • US10307358
    • 2002-12-02
    • Yukinori Kashio
    • Yukinori Kashio
    • G09G328
    • G09G3/2932G09G3/2948G09G2320/0228
    • A method for driving a surface-discharge AC (alternating current)-type PDP (Plasma Display Panel) is provided which is capable of shortening a scanning period by securing a wide range in which a voltage to induce sustaining discharge can be set without causing flicker to occur and without causing black luminance to be increased. A sub-field is made up of a resetting period, a scanning period, a wall charge forming period, and a sustaining period. During the scanning period, time interval between scanning pulses is shortened. During the wall charge forming period, each of common electrodes and data electrodes is made to be at a ground potential and a wall charge forming pulse having a same potential as that of a scanning pulse is applied to all scanning electrodes. The time interval between wall charge forming pulses is for example 3 &mgr;sec to 50 &mgr;sec. This causes space charges being left in a display cell to be attracted on each of electrodes, whereby wall charges build up.
    • 提供了一种用于驱动表面放电AC(交流)型PDP(等离子体显示面板)的方法,其能够通过确保可以设置用于引起持续放电的电压而不引起闪烁的宽范围来缩短扫描周期 发生并且不会引起黑亮度增加。 子场由复位周期,扫描期间,壁电荷形成期间和持续期间构成。 在扫描期间,扫描脉冲之间的时间间隔缩短。 在壁电荷形成期间,使公共电极和数据电极各自处于接地电位,并且将具有与扫描脉冲相同的电位的壁电荷形成脉冲施加到所有扫描电极。 壁电荷形成脉冲之间的时间间隔例如是3个字节到50个字节。 这导致显示单元中剩余的空间电荷被吸引到每个电极上,从而产生壁电荷。