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1. 发明授权

US09465559B2 System and method for emulating many time programmable memory 有权
标题翻译：用于仿真许多时间可编程存储器的系统和方法
公开(公告)号：US09465559B2
公开(公告)日：2016-10-11
申请号：US14874972
申请日：2015-10-05
申请人： TEGO, INC.
发明人： Timothy P. Butler , Javier Berrios , Steve Beckhardt , Robert W. Hamlin , Larry Moore , David Puleston , Leonid Mats
IPC分类号： H04Q5/22 , G08B13/14 , G11C11/12 , G11C11/00 , G11C11/34 , G11C7/00 , G06F3/06 , G06K7/00 , G06K19/07 , H04L29/08 , G06K7/10 , G06K19/073
CPC分类号： G06F3/0679 , G06F3/0604 , G06F3/0659 , G06K7/0008 , G06K7/10198 , G06K7/10366 , G06K19/0722 , G06K19/0723 , G06K19/073 , H04L67/04 , H04L67/12
摘要： In embodiments of the present invention improved capabilities are described for emulating multiple-time programmable memory utilizing one-time programmable memory, the memory comprising a plurality of one time programmable (OTP) memory locations for storing information, the plurality of OTP memory locations configured to operate as a single emulated many time programmable (eMTP) memory location, wherein the plurality of OTP memory locations operating as an eMTP memory location are associated with one address, the one address readable and writable.
摘要翻译：在本发明的实施例中，描述了用于使用一次性可编程存储器来仿真多时间可编程存储器的改进的能力，所述存储器包括用于存储信息的多个一次可编程（OTP）存储器位置，所述多个OTP存储器位置被配置为作为单个仿真许多时间可编程（eMTP）存储器位置操作，其中作为eMTP存储器位置操作的多个OTP存储器位置与一个地址相关联，一个地址是可读写的。

2. 发明申请

US20090021975A1 METHOD AND MEDIA FOR IMPROVING FERROELECTRIC DOMAIN STABILITY IN AN INFORMATION STORAGE DEVICE 失效
标题翻译：用于改善信息存储设备中的电磁域稳定性的方法和媒体
公开(公告)号：US20090021975A1
公开(公告)日：2009-01-22
申请号：US11778571
申请日：2007-07-16
申请人： Valluri Ramana Rao , Li-Peng Wang , Qing Ma , Byong Man Kim
发明人： Valluri Ramana Rao , Li-Peng Wang , Qing Ma , Byong Man Kim
IPC分类号： G11C11/12 , B32B15/04 , H01L21/62
CPC分类号： G11B9/02 , Y10S977/947
摘要： A media for an information storage device comprises a substrate of single-crystal silicon, a buffer layer of an epitaxial single crystal insulator formed over the substrate, a bottom electrode layer of an epitaxial single crystal conductor formed over the buffer layer, a ferroelectric layer of an epitaxial single crystal ferroelectric material formed over the bottom electrode layer, and an overlayer of an epitaxial single crystal material formed over the ferroelectric layer. Dipole charges generally having a first orientation exist at an interface between the bottom electrode layer and the ferroelectric layer includes, while dipole charges generally having a second orientation opposite the first orientation exist at an interface between the ferroelectric layer and the overlayer includes.
摘要翻译：用于信息存储装置的介质包括单晶硅衬底，形成在衬底上的外延单晶绝缘体的缓冲层，形成在缓冲层上的外延单晶导体的底电极层，形成在缓冲层上的铁电层形成在底部电极层上的外延单晶铁电材料，以及形成在铁电体层上的外延单晶材料的覆层。通常具有第一取向的偶极电荷存在于底电极层和铁电层之间的界面处，其中通常具有与第一取向相反的第二取向的偶极电荷存在于铁电层和覆层之间的界面处。

3. 发明授权

US5870328A Bistable magnetic element and method of manufacturing the same 失效
标题翻译：双稳态磁性元件及其制造方法
公开(公告)号：US5870328A
公开(公告)日：1999-02-09
申请号：US709907
申请日：1996-09-09
申请人： Kaneo Mohri
发明人： Kaneo Mohri
IPC分类号： G11C11/12 , G01R33/02 , G11C11/14 , G11C11/155 , H01F1/03 , H01F1/14 , H01F1/153 , H01F10/13 , H01F21/00 , H01L43/08
CPC分类号： G11C11/155 , G01R33/02 , G11C11/14 , H01F1/0304 , H01F1/15391 , H01F10/132
摘要： In a bistable magnetic element, a pulse current or a dc-biased high frequency current is supplied to a soft magnetic material which has a helical magnetic anisotropy. As a result, the magnitude of a voltage induced across the soft magnetic material abruptly changes with respect to variation in an external magnetic field.
摘要翻译：在双稳态磁性元件中，向具有螺旋磁各向异性的软磁材料提供脉冲电流或直流偏置高频电流。结果，软磁材料两端的电压的大小相对于外部磁场的变化而突然变化。

4. 发明授权

US3275997A Magnetic information storage unit utilizing conductive ring coupling 失效
标题翻译：磁信息存储单元利用导电环耦合
公开(公告)号：US3275997A
公开(公告)日：1966-09-27
申请号：US21839962
申请日：1962-08-21
申请人： BELL TELEPHONE LABOR INC
发明人： BOBECK ANDREW H
IPC分类号： G11C11/12
CPC分类号： G11C11/12

5. 发明授权

US3163855A Magnetic memory circuits 失效
公开(公告)号：US3163855A
公开(公告)日：1964-12-29
申请号：US85863659
申请日：1959-12-10
申请人： BELL TELEPHONE LABOR INC
发明人： BOBECK ANDREW H
IPC分类号： G11C7/00 , G11C11/12 , G11C11/14
CPC分类号： G11C11/12 , G11C7/00 , G11C11/14

6. 发明授权

US3069661A Magnetic memory devices 失效
标题翻译：磁存储器件
公开(公告)号：US3069661A
公开(公告)日：1962-12-18
申请号：US69047857
申请日：1957-10-16
申请人： BELL TELEPHONE LABOR INC
发明人： GIANOLA UMBERTO F
IPC分类号： G11C11/04 , G11C11/10 , G11C11/12
CPC分类号： G11C11/10 , G11C11/04 , G11C11/12

7. 发明授权

US11264074B2 Time-based access of a memory cell 有权
公开(公告)号：US11264074B2
公开(公告)日：2022-03-01
申请号：US17354672
申请日：2021-06-22
申请人： Micron Technology, Inc.
发明人： Umberto Di Vincenzo
IPC分类号： G11C11/12 , G11C11/22 , G11C11/56 , G11C11/00
摘要： Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

8. 发明授权

US08248835B2 Semiconductor memory and test method for the semiconductor memory 失效
标题翻译：半导体存储器的半导体存储器和测试方法
公开(公告)号：US08248835B2
公开(公告)日：2012-08-21
申请号：US12718800
申请日：2010-03-05
申请人： Tadashi Miyakawa , Daisaburo Takashima
发明人： Tadashi Miyakawa , Daisaburo Takashima
IPC分类号： G11C11/12
CPC分类号： G11C29/50 , G11C11/22 , G11C29/12005 , G11C29/1201 , G11C2029/1204
摘要： Semiconductor memory contains memory cells having ferroelectric capacitors and cell transistors, bit lines connected to memory cells, word lines connected to gate electrodes of cell transistors, plate lines connected to one of two electrodes of ferroelectric capacitors, sense amplifiers connected between each pair of bit lines. Further, a test pad is provided in order to apply an external voltage to each of bit lines, test transistors are provided corresponding to bit lines respectively, each of test transistors is connected between the test pad and each of bit lines, a fatigue test bias circuit is connected to a first node located between the test pad and test transistors. Test transistors are shared in a first test to apply a first voltage to ferroelectric capacitors from an outside via the test pad and a second test to apply a second voltage to ferroelectric capacitors from the fatigue test bias circuit.
摘要翻译：半导体存储器包括具有铁电电容器和单元晶体管的存储单元，连接到存储单元的位线，连接到单元晶体管的栅电极的字线，连接到铁电电容器的两个电极之一的板线，连接在每对位线之间的读出放大器。此外，为了对每个位线施加外部电压，提供了测试焊盘，分别对应于位线提供了测试晶体管，每个测试晶体管连接在测试焊盘和每个位线之间，疲劳测试偏置电路连接到位于测试焊盘和测试晶体管之间的第一节点。测试晶体管在第一测试中被共享，以通过测试焊盘从外部施加第一电压到铁电电容器，以及从疲劳测试偏置电路向铁电电容器施加第二电压的第二测试。

9. 发明授权

US07242602B2 Semiconductor memory devices having conductive line in twisted areas of twisted bit line pairs 失效
标题翻译：半导体存储器件在绞合位线对的扭转区域具有导线
公开(公告)号：US07242602B2
公开(公告)日：2007-07-10
申请号：US11002034
申请日：2004-12-02
申请人： Chang-Ho Lee , Jong-Hyun Choi
发明人： Chang-Ho Lee , Jong-Hyun Choi
IPC分类号： G11C5/08 , G11C5/06 , G11C11/12
CPC分类号： G11C11/4097 , G11C5/14 , G11C7/02 , Y10S257/907
摘要： A semiconductor memory device includes spaced apart twisted bit line pairs, a respective one of which includes a spaced apart twisted area. A conductive line overlaps the respective twisted areas of the spaced apart twisted line pairs. The conductive line can extend parallel to the memory device word lines, and can provide a power supply ground and/or signal line.
摘要翻译：半导体存储器件包括间隔开的扭曲位线对，其相应的一个包括间隔开的扭曲区域。导线与间隔开的扭绞线对的相应扭曲区域重叠。导线可以平行于存储器件字线延伸，并且可以提供电源接地和/或信号线。

10. 发明授权

US5508954A Method and apparatus for reduced fatigue in ferroelectric memory 失效
标题翻译：铁电存储器疲劳减少的方法和装置
公开(公告)号：US5508954A
公开(公告)日：1996-04-16
申请号：US395582
申请日：1995-02-27
申请人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： G11C14/00 , G11C11/22 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792 , G11C11/12
CPC分类号： G11C11/22 , G11C11/223 , G11C11/2293
摘要： A method and apparatus for programming ferroelectric memory cells which reduces polarizability fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors and transistors. Alteration of the pulse width duty cycle associated with signals used to switch ferroelectric device polarization is shown to reduce polarizability fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Methods and apparatus for producing a signal pulse duty cycle in the range 2-30% is disclosed and shown to improve the useful life of the ferroelectric material.
摘要翻译：一种用于编程铁电存储器单元的方法和装置，其降低与诸如铁电电容器和晶体管之类的存储单元相关联的铁电体器件的开关极化的极化率疲劳效应。显示与用于切换铁电体器件极化的信号相关联的脉冲宽度占空比的改变，以降低铁电材料的极化率疲劳，从而增加铁电存储器单元的使用寿命。公开并示出了用于产生2-30％范围内的信号脉冲占空比的方法和装置，以改善铁电材料的使用寿命。

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