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1. 发明授权

US06654439B1 High speed linear feedback shift register 有权
标题翻译：高速线性反馈移位寄存器
公开(公告)号：US06654439B1
公开(公告)日：2003-11-25
申请号：US09873512
申请日：2001-06-04
申请人： Steve Kommrusch
发明人： Steve Kommrusch
IPC分类号： G11C1900
CPC分类号： H03K23/54 , H03K23/665
摘要： An apparatus and method for providing a high speed linear feedback shift register is disclosed. The high speed linear feedback shift register of the present invention comprises multiplexer flip flop circuits. The multiplexer gate on the input of each flip flop circuit is the only gate between each pair of flip flop circuits of the present invention. The linear feedback shift register of the present invention is capable of operating as a counter that does not need to be reset. The linear feedback shift register of the present invention may be used as a clock divider circuit.
摘要翻译：公开了一种用于提供高速线性反馈移位寄存器的装置和方法。本发明的高速线性反馈移位寄存器包括多路复用器触发电路。每个触发器电路的输入上的多路复用器门是本发明的每对触发器电路之间的唯一栅极。本发明的线性反馈移位寄存器能够作为不需要复位的计数器进行操作。本发明的线性反馈移位寄存器可以用作时钟分频电路。

2. 发明授权

US06646465B2 Programmable logic device including bi-directional shift register 有权
公开(公告)号：US06646465B2
公开(公告)日：2003-11-11
申请号：US10072461
申请日：2002-02-07
申请人： Ankur Bal
发明人： Ankur Bal
IPC分类号： G11C1900
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/17736
摘要： A programmable logic device may include a programmable interconnect structure and a plurality of configurable logic elements including data latches interconnected by the interconnect structure. At least one of the configurable logic elements may be configurable as both a shift register and a lookup table. Also, the shift register may be enabled to operate as a bi-directional shift register by the inclusion of a first circuit for configuring the data latches either as series-connected inverters during a shift operation or as data latches after each shift operation. A second circuit for selecting a direction of shifting may also be included, as well as a third circuit for supplying data to the input of the shift register as determined by the direction of shifting.

3. 发明授权

US06490332B1 High speed, low-power shift register and circuits and methods using the same 有权
标题翻译：高速，低功耗移位寄存器及电路及使用方法
公开(公告)号：US06490332B1
公开(公告)日：2002-12-03
申请号：US09918616
申请日：2001-07-30
申请人： Shyam S Somayajula
发明人： Shyam S Somayajula
IPC分类号： G11C1900
CPC分类号： G11C19/28 , G11C19/00
摘要： A shift register includes a plurality of shift register stages having inputs and outputs coupled to form a chain. Each stage includes enable and disable control inputs, with an output of a selected one of the stages coupled to the enable input of a stage a selected number of stages ahead in the chain and to the disable input of a stage a selected number of stages behind in the chain.
摘要翻译：移位寄存器包括多个移位寄存器级，其具有耦合以形成链的输入和输出。每个级包括启用和禁用控制输入，其中所选择的一个级的输出耦合到级的使能输入，在链中的选定数量级的阶段，以及阶段的禁用输入，所选择的级数落后在链中。

4. 发明授权

US06418182B1 Bi-directional shift register having bi-directional shift function without deteriorating data with a reduced number of elements 有权
标题翻译：具有双向移位功能的双向移位寄存器，而不会使数量减少的元件恶化数据
公开(公告)号：US06418182B1
公开(公告)日：2002-07-09
申请号：US09239111
申请日：1999-01-28
申请人： Noriaki Suyama , Yasunori Okimura
发明人： Noriaki Suyama , Yasunori Okimura
IPC分类号： G11C1900
CPC分类号： G11C19/28 , G11C19/00
摘要： A bi-directional shift register comprises flip-flops connected to first switches and second switches. Third switches are connected in sequence and between the respective flip-flops. The third switches are on-off controlled in accordance with a CLK signal in order to periodically transition from low to high or from high to low. The shift register opens the second switches during the low duration of the REV signal and opens and closes the first switches in accordance with clocking of the CLK signal to shift data in the forward direction. The shift register opens the first switches during the high duration of the REV signal and opens and closes the second switches in accordance with the clocking of the CLK signal to shift data in the reverse direction.
摘要翻译：双向移位寄存器包括连接到第一开关和第二开关的触发器。第三开关依次连接在相应的触发器之间。第三开关根据CLK信号进行开关控制，以便从低到高或从高到低地周期性地转换。移位寄存器在REV信号的低持续时间期间打开第二开关，并且根据CLK信号的时钟来打开和闭合第一开关以向前移动数据。移位寄存器在REV信号的高持续时间期间打开第一开关，并且根据CLK信号的时钟打开和闭合第二开关以沿相反方向移位数据。

5. 发明授权

US06339631B1 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US06339631B1
公开(公告)日：2002-01-15
申请号：US09517267
申请日：2000-03-02
申请人： Ju Cheon Yeo , Jin Sang Kim
发明人： Ju Cheon Yeo , Jin Sang Kim
IPC分类号： G11C1900
CPC分类号： G11C19/28 , G11C19/184
摘要： A shift register that is suitable for reducing the required number of clock signals as well as simplifying the configuration of an external control circuit uses a plurality of stages connected, in series, to a start pulse input line. In each stage, an output circuit responds to a first control signal to apply any one of first and second clock signals to a row line of a liquid crystal cell array and thus to charge the low line of the liquid crystal cell array, and responds to a second control signal to discharge a voltage at the row line. An output circuit responds to a clock signal different from any one of the start pulse and an output signal of the previous stage to generate the first control signal, and responds to a clock signal different from the first control signal to generate the second control signal.
摘要翻译：适于减少所需数量的时钟信号的移位寄存器以及简化外部控制电路的配置使用串联连接到起始脉冲输入线的多个级。在每个阶段，输出电路响应于第一控制信号，以将第一和第二时钟信号中的任何一个施加到液晶单元阵列的行线，从而对液晶单元阵列的低线进行充电，并响应于第二控制信号，以排出行线上的电压。输出电路响应与前一级的起始脉冲和输出信号中的任何一个不同的时钟信号，以产生第一控制信号，并响应与第一控制信号不同的时钟信号以产生第二控制信号。

6. 发明授权

US06243435B1 System and method for storing digital data utilizing a resonant tunneling diode bridge 有权
标题翻译：使用谐振隧道二极管桥存储数字数据的系统和方法
公开(公告)号：US06243435B1
公开(公告)日：2001-06-05
申请号：US09484501
申请日：2000-01-18
申请人： Tom P. E. Broekaert
发明人： Tom P. E. Broekaert
IPC分类号： G11C1900
CPC分类号： B82Y10/00 , G11C19/00 , G11C19/12 , G11C2211/5614
摘要： A system for storing digital data includes an input circuit, a clock circuit, and a bridge. The input circuit is coupled to receive an input signal. The clock circuit receives and transmits a clock signal. The bridge stores the digital data and includes a plurality of negative differential resistance devices. The bridge connects to the input circuit and the clock circuit.
摘要翻译：用于存储数字数据的系统包括输入电路，时钟电路和桥。输入电路被耦合以接收输入信号。时钟电路接收和发送时钟信号。桥接器存储数字数据并且包括多个负差分电阻器件。该桥连接到输入电路和时钟电路。

7. 发明授权

US06829322B2 Shift-register circuit and shift-register unit 有权
标题翻译：移位寄存器电路和移位寄存器单元
公开(公告)号：US06829322B2
公开(公告)日：2004-12-07
申请号：US10617782
申请日：2003-07-14
申请人： Jun-Ren Shih , Shang-Li Chen , Bo-Wen Wang , Jan-Ruei Lin
发明人： Jun-Ren Shih , Shang-Li Chen , Bo-Wen Wang , Jan-Ruei Lin
IPC分类号： G11C1900
CPC分类号： G11C19/00 , G11C19/28
摘要： A shift-register unit. The first transistor includes a first source/drain coupled to a first terminal, a second source/drain, and a first gate coupled to a reset signal to stop the shift-register unit outputting a pulse signal. The second transistor includes a third source/drain coupled to the second source/drain, a fourth source/drain coupled to a second terminal, and a second gate coupled to a setting signal to initial the shift-register unit. The third transistor includes a fifth source/drain coupled to an output terminal, a third gate coupled to the second source/drain and a sixth source/drain coupled to a clock signal to start outputting the pulse signal. The fourth transistor includes a seventh source/drain coupled to the first terminal, an eighth source/drain coupled to the output terminal and a fourth gate coupled to a refresh signal to set a voltage level of the shift-register unit in a standby mode.
摘要翻译：移位寄存器单元。第一晶体管包括耦合到第一端子的第一源极/漏极，第二源极/漏极以及耦合到复位信号的第一栅极，以停止移位寄存器单元输出脉冲信号。第二晶体管包括耦合到第二源极/漏极的第三源极/漏极，耦合到第二端子的第四源极/漏极和耦合到设置信号的第二栅极以初始化移位寄存器单元。第三晶体管包括耦合到输出端的第五源极/漏极，耦合到第二源极/漏极的第三栅极和耦合到时钟信号的第六源极/漏极，以开始输出脉冲信号。第四晶体管包括耦合到第一端子的第七源极/漏极，耦合到输出端子的第八源极/漏极和耦合到刷新信号的第四栅极，以将待机模式中的移位寄存器单元的电压电平设置。

8. 发明授权

US06813332B2 Pulse output circuit, shift register and electronic equipment 有权
标题翻译：脉冲输出电路，移位寄存器和电子设备
公开(公告)号：US06813332B2
公开(公告)日：2004-11-02
申请号：US10756428
申请日：2004-01-14
申请人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
发明人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
IPC分类号： G11C1900
CPC分类号： G11C19/28 , G09G3/3688 , G09G2310/0275 , G11C19/00
摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node &agr; is raised. When the potential of the node &agr; reaches (VDD−VthN), the node &agr; becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 On, while the potential of the node &agr; of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.
摘要翻译：一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为高于（VDD + VthN）。因此，输出节点的电位升高到VDD，而不会由于TFT105的阈值电压引起电压降。然后，后级的输出被输入到TFT 103，使TFT 103导通，而电位的TFT102和106的节点α的下降以使TFT 105关闭。结果，输出节点的电位变为低电平。

9. 发明授权

US06778626B2 Bi-directional shift-register circuit 有权
标题翻译：双向移位寄存器电路
公开(公告)号：US06778626B2
公开(公告)日：2004-08-17
申请号：US10406026
申请日：2003-04-02
申请人： Jian-Shen Yu
发明人： Jian-Shen Yu
IPC分类号： G11C1900
CPC分类号： G11C19/28 , G11C19/00
摘要： A bi-directional shift-register circuit for outputting data in different turns according to a switching signal. Each shift-register unit includes a first input terminal, a second input terminal, an output terminal and a clock input terminal for receiving the clock signal. The first switching circuit is coupled to the output terminal of the pre-stage shift-register unit, the output terminal of the next-stage shift-register unit and the switching signal, and outputs the signal of the output terminal of the pre-stage shift-register unit to the first input terminal of the present-stage shift-register unit and outputs the signal of the output terminal of the next-stage shift-register unit to the second input terminal of the present-stage shift-register unit when the switching signal is at a first voltage level, and outputs the signal of the output terminal of the next-stage shift-register unit to the first input terminal of the present-stage shift-register unit and outputs the signal of the output terminal of the pre-stage shift-register unit to the second input terminal of the present-stage shift-register unit when the switching signal is at a second voltage level.
摘要翻译：一种用于根据切换信号输出不同匝数的数据的双向移位寄存器电路。每个移位寄存器单元包括用于接收时钟信号的第一输入端，第二输入端，输出端和时钟输入端。第一开关电路耦合到前级移位寄存器单元的输出端子，下一级移位寄存器单元的输出端子和开关信号，并输出前级输出端子的输出端子的信号移位寄存器单元发送到当前级移位寄存器单元的第一输入端，并且将下一级移位寄存器单元的输出端的信号输出到当前级移位寄存器单元的第二输入端，当开关信号处于第一电压电平，并且将下一级移位寄存器单元的输出端子的信号输出到当前级移位寄存器单元的第一输入端子，并将输出端子的信号输出到当开关信号处于第二电压电平时，将前级移位寄存器单元传送到当前级移位寄存器单元的第二输入端。

10. 发明授权

US06556647B1 Phase locked loop clock divider utilizing a high speed programmable linear feedback shift register with a two stage pipeline feedback path 有权
标题翻译：锁相环时钟分频器利用具有两级流水线反馈路径的高速可编程线性反馈移位寄存器
公开(公告)号：US06556647B1
公开(公告)日：2003-04-29
申请号：US10137079
申请日：2002-05-01
申请人： Karthik Reddy Neravetla
发明人： Karthik Reddy Neravetla
IPC分类号： G11C1900
CPC分类号： H03K23/665 , H03K23/54
摘要： An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register with a two stage pipeline in its feedback path. A plurality of “pre-load” flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop circuits and multiplexers. The PLFF circuits hold pre-calculated initial LFSR sequence values to be loaded into the LFSR flip flop circuits. The load enable signal to the PLFF multiplexers and to the LFSR multiplexers is low for three successive input clock cycles. The present invention is capable of operating at high frequencies due to a shortened timing critical feedback path.
摘要翻译：公开了一种用于在其反馈路径中提供具有双级管线的高速线性反馈移位寄存器的锁相环时钟分频器电路的装置和方法。多个“预加载”触发器（PLFF）电路和多路复用器耦合到多个线性反馈移位寄存器（LFSR）触发器电路和多路复用器。 PLFF电路将预先计算的初始LFSR序列值保存到LFSR触发器电路中。对于三个连续的输入时钟周期，到PLFF多路复用器和LFSR复用器的加载使能信号为低电平。本发明能够由于缩短的定时关键反馈路径而在高频下运行。

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