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1. 发明申请

US20160164533A1 FREQUENCY DIVIDER AND PHASE-LOCKED LOOP INCLUDING THE SAME 有权
标题翻译：频率分路器和相位锁定环路，包括它们
公开(公告)号：US20160164533A1
公开(公告)日：2016-06-09
申请号：US14887101
申请日：2015-10-19
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Dalun ZHAI , Jun HU
IPC分类号： H03L7/18 , H03L7/091
CPC分类号： H03L7/183 , H03K21/00 , H03K23/00 , H03K23/40 , H03K23/42 , H03K23/54 , H03K23/665
摘要： A frequency divider includes a first shifter and a second shifter. The first shifter includes first to M-th clock control components connected together to form a first ring. The control components in the first shifter are controlled by an input clock signal such that signals are shifted along the first ring. An output of selected clock control components in the first shifter is provided as a carry signal of the first shifter. The second shifter includes first to N-th clock control components connected together to form a second ring. The control components in the second shifter are controlled by the carry signal of the first shifter such that the signals are shifted along the second ring. An output of selected clock control components in the second shifter is provided as a carry signal of the second shifter. M and N are integers greater than one.
摘要翻译：分频器包括第一移位器和第二移位器。第一移位器包括连接在一起以形成第一环的第一至第M时钟控制部件。第一移位器中的控制部件由输入时钟信号控制，使得信号沿第一环移动。第一移位器中的选择的时钟控制分量的输出被提供作为第一移位器的进位信号。第二移位器包括连接在一起以形成第二环的第一至第N时钟控制部件。第二移位器中的控制部件由第一移位器的进位信号控制，使得信号沿着第二环移动。第二移位器中所选择的时钟控制部件的输出被提供作为第二移位器的进位信号。 M和N是大于1的整数。

2. 发明申请

US20150207510A1 HIGH-SPEED FREQUENCY DIVIDER 有权
标题翻译：高速分路器
公开(公告)号：US20150207510A1
公开(公告)日：2015-07-23
申请号：US14160201
申请日：2014-01-21
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： FERDINANDO PACE
IPC分类号： H03K21/10
CPC分类号： H03K21/10 , H03K23/40 , H03K23/54 , H03K23/68
摘要： A programmable high-speed frequency divider architecture is provided that is programmable to divide an input clock signal frequency by a selectable division N. The frequency divider architecture has a shift register circuit having N/2 shift register stages, connected in series when N is an even integer and trunc[N/2]+1 shift register stages when N is an odd integer. The frequency divider architecture includes a feedback logic circuit that performs a logical NAND of the output clock signal with the logical ORed result of a pre-output signal provided from a shift register stage prior to the output stage and another signal that indicates whether the selectable divisor N is odd or even.
摘要翻译：提供了一种可编程的高速分频器架构，其可编程以通过可选择分段N来分频输入时钟信号频率。分频器架构具有移位寄存器电路，其具有N / 2个移位寄存器级，当N为当N是一个奇整数时，甚至整数和trunc [N / 2] +1个移位寄存器级。分频器架构包括反馈逻辑电路，其在输出级之前从移位寄存器级提供的预输出信号的逻辑或运算结果执行输出时钟信号的逻辑NAND，以及指示是否可选择除数的另一信号 N是奇数或偶数。

3. 发明申请

US20150055726A1 FRACTIONAL FREQUENCY DIVIDING CIRCUIT AND TRANSMITTER 有权
标题翻译：分频电路和发射机
公开(公告)号：US20150055726A1
公开(公告)日：2015-02-26
申请号：US14167726
申请日：2014-01-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takafumi Yamaji , Tsuneo Suzuki
IPC分类号： H03B19/14 , H04B1/04
CPC分类号： H03B19/14 , H03K23/54 , H04B1/04 , H04B2001/0491
摘要： According to one embodiment, there is provided a fractional frequency dividing circuit including an integral frequency dividing circuit and an adjustment circuit. The integral frequency dividing circuit is configured to convert a reference signal to K (K is a positive integer) phase signals. Each of the K phase signals has a frequency of one nth (n is a positive integer) of the reference signal and has different phases from each other. The adjustment circuit is configured to weighting-add a plurality of signals corresponding to the K phase signals and generate a fractional-frequency-divided signal. The fractional-frequency-divided signal has a frequency of m times (m is a positive integer that is not multiplies of n) of each of the plurality of phase signals.
摘要翻译：根据一个实施例，提供了一种包括积分分频电路和调节电路的分数分频电路。积分分频电路被配置为将参考信号转换为K（K是正整数）相位信号。 K个相位信号中的每一个具有参考信号的第n个（n为正整数）的频率，并且具有彼此不同的相位。调整电路被配置为对与K个相位信号相对应的多个信号进行加权加法，并生成分数分频信号。分数分频信号具有多个相位信号中的每一个的m倍的频率（m是不与n相乘的正整数）。

4. 发明授权

US08275326B2 System and method for low noise output divider and buffer having low current consumption 有权
标题翻译：具有低电流消耗的低噪声输出分频器和缓冲器的系统和方法
公开(公告)号：US08275326B2
公开(公告)日：2012-09-25
申请号：US11837003
申请日：2007-08-10
申请人： Rajasekhar Pullela , Sohrab Samadian
发明人： Rajasekhar Pullela , Sohrab Samadian
IPC分类号： H04B1/40
CPC分类号： H03L7/099 , H03K23/54
摘要： A low noise divider includes a voltage controlled oscillator (VCO) having a first frequency output, a frequency divider configured to receive the first frequency output and configured to provide a second frequency output; and a buffer circuit configured to receive the first frequency output and the second frequency output, the buffer circuit configured to provide the second frequency output as an output of the low noise divider, where a phase noise of the second frequency output is dependent only on a phase noise of the first frequency output.
摘要翻译：低噪声分压器包括具有第一频率输出的压控振荡器（VCO），配置成接收第一频率输出并被配置为提供第二频率输出的分频器; 以及缓冲电路，被配置为接收所述第一频率输出和所述第二频率输出，所述缓冲电路被配置为提供所述第二频率输出作为所述低噪声分频器的输出，其中所述第二频率输出的相位噪声仅依赖于第一频率输出的相位噪声。

5. 发明授权

US08217688B2 Method and device for dividing a frequency signal 有权
公开(公告)号：US08217688B2
公开(公告)日：2012-07-10
申请号：US13357888
申请日：2012-01-25
申请人： John Kevin Behel , Reuben Pascal Nelson
发明人： John Kevin Behel , Reuben Pascal Nelson
IPC分类号： H03B19/00
CPC分类号： H03K21/38 , H03K23/54
摘要： A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a higher counting capacity than the first counter. The output occurs when the first counter reaches a first number of count cycles. The method also includes generating a third signal having a high cycle and a low cycle, which are determined at least as a function of the first number of count cycles. Depending on a desired division ratio, the high and low cycles may also be a function of a second number of count cycles associated with the second counter. The third signal has a frequency lower than the first frequency.

6. 发明申请

US20120008733A1 COUNTING CIRCUIT AND ADDRESS COUNTER USING THE SAME 有权
标题翻译：计数电路和地址计数器
公开(公告)号：US20120008733A1
公开(公告)日：2012-01-12
申请号：US13237763
申请日：2011-09-20
申请人： Mi Sun YOON , Chul Woo YANG , Sang Oh LIM
发明人： Mi Sun YOON , Chul Woo YANG , Sang Oh LIM
IPC分类号： H03K23/00
CPC分类号： H03K21/38 , G11C8/04 , H03K23/54
摘要： A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal. Each of the first to fourth FFs receives a signal at a corresponding input terminal. And each of the first to fourth FFs outputs a signal at a corresponding output terminal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals.
摘要翻译：计数电路包括第一至第五触发器（FF）和逻辑运算单元。第一至第四FF中的每一个具有基于通过4位设置终端输入的预设控制信号的初始值。第一至第四FF中的每一个在相应的输入端接收信号。并且第一至第四FF中的每一个根据时钟信号在相应的输出端输出信号。第五FF耦合到第四FF的输出端子，并被配置为与时钟信号同步地输出第四FF的输出信号。逻辑运算单元逻辑组合第二至第四FF的输出信号，并输出第一和第二计数信号。

7. 发明申请

US20110293062A1 Method and Apparatus for Rapid Synchronization of Shift Register Related Symbol Sequences 有权
标题翻译：移位寄存器相关符号序列快速同步的方法和装置
公开(公告)号：US20110293062A1
公开(公告)日：2011-12-01
申请号：US13118767
申请日：2011-05-31
申请人： Peter Lablans
发明人： Peter Lablans
IPC分类号： H03K21/40
CPC分类号： H04L7/0091 , G06F7/584 , H03K23/54 , H04J13/0029 , H04J13/0033 , H04J13/0074 , H04J13/10
摘要： A sequence generator implemented on a receiver is synchronized with a sequence generator at a transmitter. The receiver receives k n-state symbols, with k>1 and n>1 wherein each of the k n-state symbols is associated with a generating state of the sequence generator at the transmitter. A processor in the receiver evaluates an n-state expression that generates an n-state symbol that is associated with a synchronized state of the receiver. Coefficients related to the n-state expression are stored on a memory and are retrieved by the processor. The synchronized state in one embodiment is part of a code hop. The sequence generator in the receiver may be part of a descrambler, of a communication device, of a data storage device and/or of an opening mechanism.
摘要翻译：在接收机上实现的序列发生器与发射机的序列发生器同步。接收机接收k个n状态符号，其中k> 1且n> 1，其中k个n状态符号中的每一个与发射机处的序列发生器的生成状态相关联。接收器中的处理器评估产生与接收器的同步状态相关联的n状态符号的n状态表达式。与n状态表达式相关的系数存储在存储器中，并由处理器检索。一个实施例中的同步状态是代码跳的一部分。接收机中的序列发生器可以是数据存储设备和/或打开机构的通信设备的解扰器的一部分。

8. 发明授权

US07999622B2 Adaptive phase noise cancellation for fractional-N phase locked loop 有权
$Adaptive phase noise cancellation for fractional-N phase locked loop$
标题翻译：分数N锁相环的自适应相位噪声消除
公开(公告)号：US07999622B2
公开(公告)日：2011-08-16
申请号：US12352293
申请日：2009-01-12
申请人： Ian Galton , Ashok Swaminathan
发明人： Ian Galton , Ashok Swaminathan
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03K23/54 , H03K23/667 , H03L7/0895 , H03L7/0898 , H03L7/093 , H03L7/193
摘要： An embodiment of the invention is a circuit for adaptive phase noise cancellation for a fractional-N PLL. A preferred embodiment employs a split loop filter architecture. Two loop filter halves separately drive half-sized parallel varactors in a voltage controlled oscillator (VCO) and also drive a differential-input lowpass frequency selective circuit, e.g., a differential-input integrator in a least mean squared (LMS) feedback loop. The output of the differential-input lowpass frequency selective circuit controls the gain matching of a phase noise cancellation path to minimize phase noise arising from quantization error associated with the sequence of divider modulus values in the fractional-N PLL. The two varactor capacitances add together in the VCO tank, so the VCO frequency depends on the common-mode loop filter voltage and is relatively insensitive to differential-mode voltage. In contrast, the differential integrator operates on the differential-mode voltage from the two loop filter halves but attenuates their common-mode voltage.
摘要翻译：本发明的实施例是用于分数N PLL的自适应相位噪声消除的电路。优选实施例采用分裂环路滤波器架构。两个环路滤波器半部分别在压控振荡器（VCO）中驱动半尺寸并联变容二极管，并且还驱动差分输入低通频率选择电路，例如在最小均方（LMS）反馈回路中的差分输入积分器。差分输入低通频率选择电路的输出控制相位噪声消除路径的增益匹配，以使与分数N PLL中的分频器模数值序列相关联的量化误差产生的相位噪声最小化。 VCO容器中的两个变容二极管电容加在一起，因此VCO频率取决于共模环路滤波器电压，对差模电压相对不敏感。相比之下，差分积分器对来自两个环路滤波器一半的差分模式电压进行操作，但会衰减其共模电压。

9. 发明授权

US07952420B2 Counting apparatus 失效
标题翻译：计数器
公开(公告)号：US07952420B2
公开(公告)日：2011-05-31
申请号：US12629889
申请日：2009-12-03
申请人： Jin-Liang Xiong
发明人： Jin-Liang Xiong
IPC分类号： H03K17/687
CPC分类号： H03K21/18 , H03K23/54
摘要： A counting apparatus includes a sampling circuit, and a counting and displaying circuit. The sampling circuit includes an interface, a first electric switch, and a second electric switch. The counting and displaying circuit includes a counter and a display tube. Seven input terminals of the display tube are connected to seven output terminals of the counter correspondingly. A clock-up counting terminal of the counter is connected to the second terminal of the second electric switch.
摘要翻译：计数装置包括采样电路和计数显示电路。采样电路包括接口，第一电开关和第二电开关。计数显示电路包括计数器和显示管。显示管的七个输入端子相应地连接到计数器的七个输出端子。计数器的时钟计数端子连接到第二电开关的第二端子。

10. 发明申请

US20100289780A1 Shift Register Turning On a Feedback Circuit According to a Signal From a Next Stage Shift 审中-公开
标题翻译：移位寄存器根据下一阶段的信号切换反馈电路
公开(公告)号：US20100289780A1
公开(公告)日：2010-11-18
申请号：US12842026
申请日：2010-07-22
申请人： Lee-Hsun Chang , Yu-Wen Lin , Chun-Ching Wei , Wei-Cheng Lin
发明人： Lee-Hsun Chang , Yu-Wen Lin , Chun-Ching Wei , Wei-Cheng Lin
IPC分类号： G09G5/00
CPC分类号： G09G3/3674 , G09G2300/0408 , G11C19/28 , H03K23/54
摘要： A shift register capable of turning on a feedback register includes a signal generating circuit for generating an output signal at an output end of the shift register according to a first clock signal while the signal generating circuit is being turned on, a driving circuit, electrically coupled to the signal generating circuit, for generating a driving signal to control the signal generating circuit according to an input signal received by an input end of the shift register, a feedback circuit, electrically coupled to a next stage shift register, for transmitting a control signal while the feedback circuit is being turned on by the next stage shift register, and a control switch, electrically coupled to the signal generating circuit and the feedback circuit, for turning off the signal generating circuit while the control switch is being turned on by the control signal transmitted from the feedback circuit.
摘要翻译：能够接通反馈寄存器的移位寄存器包括：信号发生电路，用于在信号发生电路导通时根据第一时钟信号在移位寄存器的输出端产生输出信号;驱动电路，电耦合用于产生驱动信号以根据由移位寄存器的输入端接收到的输入信号来控制信号发生电路，电耦合到下一级移位寄存器的反馈电路，用于发送控制信号同时反馈电路被下一级移位寄存器导通，以及控制开关，电耦合到信号发生电路和反馈电路，用于在控制开关由控制器接通的同时关闭信号发生电路信号从反馈电路发送。

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