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1. 发明授权

US09472754B2 In-situ annealing to improve the tunneling magneto-resistance of magnetic tunnel junctions 有权
标题翻译：原位退火以改善磁隧道结的隧道磁阻
公开(公告)号：US09472754B2
公开(公告)日：2016-10-18
申请号：US15062725
申请日：2016-03-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guohan Hu , Daniel C. Worledge
IPC分类号： H01L29/96 , H01L43/12 , H01L27/105 , H01L27/22
CPC分类号： H01L43/12 , H01L27/1052 , H01L27/222 , H01L27/228 , H01L43/08
摘要： Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure.
摘要翻译：实施例涉及包括由垂直磁各向异性（PMA）参考层和界面参考层形成的参考层的磁性隧道结（MTJ）存储单元。 MTJ还包括位于界面参考层和自由层之间的自由层和隧道屏障。隧道势垒被配置为使得电子能够穿过界面参考层和自由层之间的隧道势垒。在隧道势垒的隧道阻挡栅格结构和界面参考层的界面参考层晶格结构之间提供了第一原位对准。在隧道势垒的隧道势垒晶格结构和自由层的自由层晶格结构之间提供第二原位对准。 PMA参考层晶格结构不与界面参考层晶格结构对齐。

2. 发明授权

US08653606B2 Semiconductor device and power conversion device using same 有权
标题翻译：半导体器件和使用其的功率转换器件
公开(公告)号：US08653606B2
公开(公告)日：2014-02-18
申请号：US13928894
申请日：2013-06-27
申请人： Hitachi, Ltd.
发明人： Masaki Shiraishi
IPC分类号： H01L29/66 , H01L29/739 , H01L29/96
CPC分类号： H01L29/7396 , H01L29/0623 , H01L29/0646 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/66348 , H01L29/7397 , H02M7/003 , H02M7/537 , H02M7/5387
摘要： It is intended to provide a semiconductor device capable to improve a controllability of dv/dt by a gate drive circuit during a turn-on switching period, while maintaining a low loss and a high breakdown voltage. Trench gates are disposed so as to have narrow distance regions and wide distance regions, wherein each of the narrow distance regions is provided with a channel region, and each of the wide distance regions is provided with trenches, each trench having an electrode electrically connected to the emitter electrode. In this manner, even if a floating-p layer is removed, it is possible to reduce a feedback capacity and maintain a breakdown voltage.
摘要翻译：旨在提供一种半导体器件，其能够在导通开关周期期间通过栅极驱动电路提高dv / dt的可控性，同时保持低损耗和高击穿电压。沟槽门设置成具有窄距离区域和宽距离区域，其中每个窄距离区域设置有沟道区域，并且每个宽距离区域设置有沟槽，每个沟槽具有电连接到发射电极。以这种方式，即使去除浮置p层，也可以减小反馈容量并维持击穿电压。

3. 发明申请

US20080224242A1 PROCESS FOR MANUFACTURING A MEMBRANE OF SEMICONDUCTOR MATERIAL INTEGRATED IN, AND ELECTRICALLY INSULATED FROM, A SUBSTRATE 有权
标题翻译：一种制造半导体材料膜的方法，集成在一个基板上并电绝缘
公开(公告)号：US20080224242A1
公开(公告)日：2008-09-18
申请号：US12047830
申请日：2008-03-13
申请人： Flavio Franceso Villa , Pietro Corona , Chantal Combi , Lorenzo Baldo , Gabriele Barlocchi
发明人： Flavio Franceso Villa , Pietro Corona , Chantal Combi , Lorenzo Baldo , Gabriele Barlocchi
IPC分类号： H01L29/96 , H01L21/02
CPC分类号： B81C1/00158
摘要： A process for manufacturing an integrated membrane made of semiconductor material includes the step of forming, in a monolithic body of semiconductor material having a front face, a buried cavity, extending at a distance from the front face and delimiting with the front face a surface region of the monolithic body, the surface region forming a membrane that is suspended above the buried cavity. The process further envisages the step of forming an insulation structure in a surface portion of the monolithic body to electrically insulate the membrane from the monolithic body; and the further and distinct step of setting the insulation structure at a distance from the membrane so that it will be positioned outside the membrane at a non-zero distance of separation.
摘要翻译：制造由半导体材料制成的集成膜的方法包括以下步骤：在具有前表面的半导体材料的整体中形成一个与前表面相距一定距离的掩埋腔，的单体，表面区域形成悬浮在掩埋腔上方的膜。该方法进一步设想在整体式主体的表面部分形成绝缘结构以将膜与整体式电绝缘的步骤; 以及将绝缘结构设置在离膜一定距离处的进一步和不同的步骤，使得其将以非零分离距离定位在膜的外部。

4. 发明申请

US20050184324A1 Storage capacitor structure and liquid crystal display device having the same 审中-公开
标题翻译：存储电容器结构和具有相同的液晶显示装置
公开(公告)号：US20050184324A1
公开(公告)日：2005-08-25
申请号：US11094884
申请日：2005-03-30
申请人： Yuan-Liang Wu , Tong-Jung Wang , Chin-Jung Kuo
发明人： Yuan-Liang Wu , Tong-Jung Wang , Chin-Jung Kuo
IPC分类号： H01L21/02 , H01L29/96
CPC分类号： H01L28/40
摘要： A storage capacitor structure comprising a first capacitor electrode on a substrate, a capacitor dielectric layer on the first capacitor electrode and a second capacitor electrode on the capacitor dielectric layer, a passivation layer on the second capacitor electrode and a pixel electrode layer on the passivation layer. The second capacitor electrode has an area smaller than the first capacitor electrode. The passivation layer has an opening that exposes a portion of the second capacitor electrode. The pixel electrode layer and the second capacitor electrode are electrically connected through the opening in the passivation layer.
摘要翻译：一种存储电容器结构，包括在基板上的第一电容器电极，所述第一电容器电极上的电容器电介质层和所述电容器电介质层上的第二电容器电极，所述第二电容器电极上的钝化层和所述钝化层上的像素电极层。第二电容器电极具有小于第一电容器电极的面积。钝化层具有露出第二电容器电极的一部分的开口。像素电极层和第二电容电极通过钝化层中的开口电连接。

5. 发明授权

US6133611A MOS semiconductor device 失效
标题翻译： MOS半导体器件
公开(公告)号：US6133611A
公开(公告)日：2000-10-17
申请号：US352780
申请日：1999-07-14
申请人： Akira Yamaguchi
发明人： Akira Yamaguchi
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/76 , H01L29/96
CPC分类号： H01L21/823814
摘要： In a CMOS circuit including a source diffusion layer and a well region which are at the same potential, a P.sup.+ -type source diffusion layer and an N.sup.+ -type substrate diffusion layer are formed in a portion corresponding to a source region in a surface area of an N-type well region. A source contact is formed on the source and substrate diffusion layers through a salicide layer to connect the diffusion layers to their upper wiring layer. Since, therefore, the source contact can be arranged closer to a P-type well region, the layout area can be reduced.
摘要翻译：在具有相同电位的源极扩散层和阱区的CMOS电路中，在对应于表面积的源极区域的部分形成有P +型源极扩散层和N +型衬底扩散层一个N型井区。通过硅化物层在源极和衬底扩散层上形成源极接触，以将扩散层连接到其上部布线层。因此，由于源极触点可以更靠近P型阱区域布置，因此可以减小布局面积。

6. 发明授权

US5959214A Strain gauge with steel substrate 失效
标题翻译：应变计与钢基材
公开(公告)号：US5959214A
公开(公告)日：1999-09-28
申请号：US995801
申请日：1997-12-22
申请人： Aparna Vaidyanthan , Robert Keith Constable , Shailendra Verma
发明人： Aparna Vaidyanthan , Robert Keith Constable , Shailendra Verma
IPC分类号： G01L1/22 , H01L29/96
CPC分类号： G01L1/2293
摘要： A strain gauge has a stainless steel substrate with a dielectric coating comprising two dielectric layers. A circuit comprising conductors, resistors and piezoresistors in a Wheatstone bridge configuration is formed on the dielectric. One dielectric layer is to adhere to the steel and a second is to form a barrier against diffusion of the first layer into the piezoresistor material. An amplification and signal conditioning circuit is applied adjacent the bridge. The steel substrate is to be welded or bolted at its marginal portions to a structure subject to strain.
摘要翻译：应变计具有不锈钢基底，其具有包括两个电介质层的电介质涂层。包括惠斯通电桥配置中的导体，电阻器和压电阻器的电路形成在电介质上。一个电介质层将粘附到钢上，其次是形成防止第一层扩散到压敏电阻材料中的屏障。在桥附近施加放大和信号调理电路。钢基材将在其边缘部分被焊接或螺栓连接到受到应变的结构。

7. 发明授权

US5511428A Backside contact of sensor microstructures 失效
标题翻译：传感器微结构背面接触
公开(公告)号：US5511428A
公开(公告)日：1996-04-30
申请号：US257716
申请日：1994-06-10
申请人： Howard D. Goldberg , Martin A. Schmidt
发明人： Howard D. Goldberg , Martin A. Schmidt
IPC分类号： B81B7/00 , G01F1/684 , G01L9/00 , G01P15/08 , H01L29/96
CPC分类号： B81B7/0061 , B81B7/007 , G01F1/6845 , G01L9/0042 , G01L9/0073 , G01P15/0802 , G01B2210/64
摘要： A sensor microstructure contact scheme is provided for making backside electrical, mechanical, fluidic, or other contact to mechanical microstructures. The contact scheme is applicable to pressure sensors, shear stress sensors, flow rate sensors, temperature sensors, resonant microactuators, and other microsensors and microactuators. The contact scheme provides a microelectromechanical sensor body and support structure for backside contact of the sensor body, and features a support wafer substrate having one or more through-wafer vias each with a lateral span on the dimension of microns and a span that is more narrow at the wafer front surface than at the wafer back surface. An insulating film covers a portion of the support wafer substrate and sidewalls of the vias--with the lateral via span at the front surface being open. The front surface of the support wafer substrate is bonded to the front surface of a sensor body wafer substrate, such that contact of the front surface of the sensor body wafer substrate may be made through the support wafer substrate vias from the back surface of the support wafer substrate. The sensor body wafer substrate is adapted to define a mechanical sensor microstructure, and comprises a plurality of isolated substrate regions, each region corresponding to one of the support wafer substrate through-wafer vias. Each such region is circumscribed by an edge of the mechanical sensor microstructure and an isolating border region. Contact made through one of the support wafer substrate through-wafer vias to the corresponding one of the sensor body substrate regions is isolated and thereby prevented from making contact to any other sensor body substrate region.
摘要翻译：提供传感器微结构接触方案用于制造机械微观结构的背面电气，机械，流体或其他接触。接触方案适用于压力传感器，剪切应力传感器，流量传感器，温度传感器，共振微致动器和其他微传感器和微型致动器。接触方案提供了用于传感器主体的背侧接触的微机电传感器主体和支撑结构，其特征在于具有一个或多个贯穿晶片通孔的支撑晶片基板，每个通孔具有微米尺寸上的横向跨度和更窄的跨度在晶片正面与晶片背面相比。绝缘膜覆盖支撑晶片基板的一部分和通孔的侧壁，其中在前表面处的横向通孔跨度是敞开的。支撑晶片基板的前表面结合到传感器体晶片基板的前表面，使得传感器体晶片基板的前表面可以通过支撑晶片基板通孔从支撑体的后表面晶圆基板。传感器体晶片衬底适于限定机械传感器微结构，并且包括多个隔离的衬底区域，每个区域对应于支撑晶片衬底通晶片通孔之一。每个这样的区域被机械传感器微结构的边缘和隔离边界区域限定。通过支撑晶片衬底通过晶片通孔中的一个到相应的一个传感器主体衬底区域的接触被隔离，从而防止与任何其它传感器主体衬底区域接触。

8. 发明授权

US5408119A Monolithic micromechanical vibrating string accelerometer with trimmable resonant frequency 失效
标题翻译：具有可调谐共振频率的单片微机械振弦加速度计
公开(公告)号：US5408119A
公开(公告)日：1995-04-18
申请号：US599131
申请日：1990-10-17
申请人： Paul Greiff
发明人： Paul Greiff
IPC分类号： G01P15/08 , G01P15/097 , G01P15/10 , H01L29/84 , H01L29/66 , H01L29/96
CPC分类号： G01P15/097 , G01P15/0802 , G01P2015/0814 , G01P2015/0831 , Y10S438/978
摘要： A monolithic, micromechanical vibrating string accelerometer with a trimmable resonant frequency is fabricated from a silicon substrate which has been selectively etched to provide a resonant structure suspended over an etched pit. The resonant structure comprises an acceleration sensitive mass and at least two flexible elements having resonant frequencies. Each of the flexible elements is disposed generally colinear with at least one acceleration sensitive axis of the accelerometer. One end of at least one of the flexible elements is attached to a tension relief beam for providing stress relief of tensile forces created during the fabrication process. Mass support beams having a high aspect ratio support the mass over the etched pit while allowing the mass to move freely in the direction colinear with the flexible elements. Also disclosed is a method for fabricating such an accelerometer with high aspect ratio tension relief and mass support beams.
摘要翻译：具有可调谐谐振频率的单片微机械振弦系统加速度计由硅衬底制成，该衬底已被选择性地蚀刻以提供悬浮在蚀刻凹坑上的谐振结构。谐振结构包括加速度敏感质量和至少两个具有谐振频率的柔性元件。每个柔性元件通常与加速度计的至少一个加速度敏感轴线共线设置。至少一个柔性元件的一端附接到张力释放梁，以提供在制造过程中产生的张力的应力消除。具有高纵横比的质量支撑梁支撑蚀刻凹坑上的质量，同时允许质量在与柔性元件的共线方向上自由移动。还公开了一种用于制造具有高纵横比张力释放和质量支撑梁的这种加速度计的方法。

9. 发明授权

US5343064A Fully integrated single-crystal silicon-on-insulator process, sensors and circuits 失效
标题翻译：完全集成的单晶硅绝缘体工艺，传感器和电路
公开(公告)号：US5343064A
公开(公告)日：1994-08-30
申请号：US169788
申请日：1988-03-18
申请人： Leland J. Spangler , Kensall D. Wise
发明人： Leland J. Spangler , Kensall D. Wise
IPC分类号： G01P15/08 , G01P15/125 , H01L27/20 , H01L29/84 , H01L27/01 , H01L29/96
CPC分类号： B81C1/00246 , G01P15/0802 , G01P15/125 , H01L27/20 , G01P2015/0828
摘要： Integrated semiconductor-on-insulator (SOI) sensors and circuits which are electrostatically bonded to a support substrate, such as glass or an oxidized silicon wafer, are disclosed. The SOI sensors and SOI circuits are both formed using a novel fabrication process which allows multiple preformed and pretested integrated circuits on a silicon wafer to be electrostatically bonded to the support substrate without exposing the sensitive active regions of the electronic devices therein to a damaging electric field. The process includes forming a composite bonding structure on top of the integrated circuits prior to the bonding step. This composite structure includes a conductive layer dielectrically isolated from the circuit devices and electrically connected to the silicon wafer, which is spaced form but laterally overlaps at least the active semiconductive regions of the circuit devices. The SOI sensors each include a transducer and at least one active electronic device, which are both made at least in part from a common layer of lightly-doped single-crystal semiconductor material grown on the silicon wafer. After the bonding step, the bulk of the single-crystal wafer is removed, leaving the epitaxial layer containing the circuits and transducers. The epitaxial layer is then patterned into isolated mesas to dielectrically isolate the electronic devices. This patterning step also exposes bond pads, allowing external connections to be readily made to the sensors and circuits. Exemplary solid-state sensors disclosed herein include a capacitive accelerometer and pressure sensor.
摘要翻译：公开了集成绝缘体上绝缘体（SOI）传感器和静电结合到诸如玻璃或氧化硅晶片之类的支撑衬底的电路。 SOI传感器和SOI电路都使用新颖的制造工艺来形成，其允许在硅晶片上的多个预成型和预测试的集成电路静电结合到支撑衬底，而不将其中的电子器件的敏感有源区域暴露于有害电场。该方法包括在结合步骤之前在集成电路的顶部上形成复合结合结构。该复合结构包括与电路器件介电隔离并与硅晶片电连接的导电层，该硅晶片与电路器件的至少有源半导体区域间隔开形式但横向重叠。 SOI传感器各自包括换能器和至少一个有源电子器件，其至少部分地由在硅晶片上生长的共同的轻掺杂单晶半导体材料层制成。在接合步骤之后，去除大部分单晶晶片，留下包含电路和换能器的外延层。然后将外延层图案化成隔离的台面以介电地隔离电子器件。该图案化步骤还暴露了接合焊盘，允许容易地对传感器和电路进行外部连接。本文公开的示例性固体传感器包括电容加速度计和压力传感器。

10. 发明授权

US5262659A Nyquist frequency bandwidth hact memory 失效
标题翻译：奈奎斯特频带宽带内存
公开(公告)号：US5262659A
公开(公告)日：1993-11-16
申请号：US928374
申请日：1992-08-12
申请人： Thomas W. Grudkowski , Donald E. Cullen
发明人： Thomas W. Grudkowski , Donald E. Cullen
IPC分类号： H01L29/765 , H03H9/02 , H01L29/84 , H01L29/96 , H01L41/08
CPC分类号： H01L29/765 , H03H9/02976
摘要： A HACT device which propagates charge packets 21 along a charge transport channel 17 by a surface acoustic wave (SAW) 14 is provided with an interdigital electrode grid 30 disposed on the upper surface of the HACT, near the charge transport channel 17, having electrodes 30 spaced a distance of one-half wavelength of the SAW. A hold voltage Vh is applied across alternating electrodes to store (i.e., stop and hold) each charge packet. When a charge packet is to be released, the hold voltage Vh is removed and the electrodes 30 are shorted together or alternatively connected through a maximum allowable impedance, thereby allowing each charge packet 21 to be stored and released by the device without having the electrodes 30 absorb the SAW electric fields. Because the electrodes 30 are spaced one-half a SAW wavelength apart, the HACT memory can store each and every charge packet 21, thereby providing a Nyquist bandwidth device. Furthermore, the electrodes 30 are made thin to reduce mechanical absorption of the SAW by the electrodes.
摘要翻译：通过表面声波（SAW）14沿着电荷传送通道17传播电荷包21的HACT装置设置有设置在HACT的上表面上的交叉指状电极栅极30，电荷传输通道17附近具有电极30 隔开SAW的二分之一波长的距离。在交替电极之间施加保持电压Vh以存储（即停止和保持）每个电荷包。当要释放电荷包时，保持电压Vh被去除，并且电极30被短路在一起，或者通过最大允许阻抗交替地连接，从而允许每个电荷包21被器件储存和释放，而不需要电极30 吸收SAW电场。因为电极30隔开一半的SAW波长，所以HACT存储器可以存储每一个电荷包21，从而提供奈奎斯特带宽装置。此外，电极30被制成薄以减少由电极对SAW的机械吸收。

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