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1. 发明申请

US20230110917A1 DETECTING WATER INGRESS IN ELECTRONIC POWER STEERING SYSTEMS 有权
公开(公告)号：US20230110917A1
公开(公告)日：2023-04-13
申请号：US17496032
申请日：2021-10-07
申请人： ZF Active Safety and Electronics US LLC
发明人： Abraham Ghafari , Mohammad Ashraf Ali
IPC分类号： B62D5/04 , G01N27/22 , H03H1/02
摘要： Systems and methods are provided for detecting water within an electronic power steering assembly. A sensor assembly includes a resistor and a water-sensitive capacitor arranged to provide a series resistor-capacitor (RC) network having a cut-off frequency that is a function of a capacitance of the water-sensitive capacitor. An oscillator provides an excitation to the series RC network having a known frequency, such that the series RC network provides an output in response to the excitation. An envelope detector receives the output of the series RC network and generates an output representing an amplitude of the output of the series RC network. A microcontroller determines if water is present within the electronic power steering assembly from the amplitude of the output of the series RC network.

2. 发明授权

US10892728B2 Virtual inductors using ferroelectric capacitance and the fabrication method thereof 有权
公开(公告)号：US10892728B2
公开(公告)日：2021-01-12
申请号：US16226747
申请日：2018-12-20
申请人： Mitsubishi Electric Research Laboratories, Inc.
发明人： Koon Hoo Teo , Pin Chun Shen , Chungwei Lin
IPC分类号： H03H1/00 , H03H3/00 , H03H7/06 , H03H1/02
摘要： Devices, system and methods a circuit, including a resistor, a normal capacitor and a ferroelectric capacitor connected in series. An input terminal to provide an input voltage across the circuit. An output terminal to deliver an output voltage taken across the normal capacitor. The circuit comprises a ferroelectric layer sandwiched between a first buffer layer and a second buffer layer. The first buffer layer contacts a portion of a first metal layer and first metal layer extends beyond the first buffer layer. A dielectric layer sandwiched between a second metal layer and a third metal layer. Such that the second metal layer extends beyond the dielectric layer and in contact with the second buffer layer. Wherein the ferroelectric capacitor is formed by the first metal layer. The ferroelectric layer sandwiched between the first buffer layer and the second buffer layer, and the second metal layer.

3. 发明申请

US20200007105A1 PROCESS-INVARIANT DELAY CELL 审中-公开
公开(公告)号：US20200007105A1
公开(公告)日：2020-01-02
申请号：US16023186
申请日：2018-06-29
申请人： QUALCOMM Incorporated
发明人： Chao SONG , Haitao CHENG , Ye LU , Dongjiang QIAO
IPC分类号： H03H7/30 , H03H1/02 , H03H3/00 , H03H7/06 , H01L49/02 , H01L23/66 , H01L23/522 , H01L23/528 , H01L23/532
摘要： An integrated circuit (IC) device includes a first resistive strip having an input terminal and an output terminal. The IC device further includes a second resistive strip having a terminal coupled to a voltage. The second resistive strip may be coplanar with the first resistive strip. The IC device further includes a capacitor formed by the first resistive strip and the second resistive strip.

4. 发明授权

US10461715B1 Mitigating power noise using a current supply 有权
公开(公告)号：US10461715B1
公开(公告)日：2019-10-29
申请号：US16196080
申请日：2018-11-20
申请人： International Business Machines Corporation
发明人： Martin Bernhard Schmidt , Thomas Strach , Hubert Harrer , Jochen Supper
IPC分类号： G06F1/28 , G06F1/30 , H03H1/02 , G06F1/26
摘要： Provided are embodiments including methods, systems, and computer-program products for mitigating power supply noise using one or more current supplies. In some embodiments, power is provided to an integrated circuit, wherein a first circuit is coupled to the integrated circuit over a first path. A variation of the current level of the integrated circuit may be determined. Additional power from a second circuit is provided to the integrated circuit may be provided based at least in part on the determined variation, wherein the second circuit is coupled to the integrated circuit over a second path.

5. 发明申请

US20190044212A1 Transmission Line Bias Resistor 审中-公开
公开(公告)号：US20190044212A1
公开(公告)日：2019-02-07
申请号：US16049889
申请日：2018-07-31
申请人： AVX Corporation
发明人： George Korony
IPC分类号： H01P5/16 , H01L23/66 , H03H1/02 , H01P3/08
摘要： Systems and methods for introducing DC bias in a radio frequency (RF) signal communicated over a transmission line are provided. In one example implementation, the RF system can include a transmission line having a first port and a second port. The transmission line can be configured to communicate an RF signal between a first port and a second port. One or more DC bias resistors can be coupled to the transmission line at a location between the first port and the second port. Each DC bias resistor can provide a path for injecting DC current to the transmission line to provide DC bias for the RF signal. Each DC bias resistor can be coupled to the transmission line via a point connection.

6. 发明授权

US10128823B2 Subthreshold metal oxide semiconductor for large resistance 有权
公开(公告)号：US10128823B2
公开(公告)日：2018-11-13
申请号：US14642309
申请日：2015-03-09
申请人： QUALCOMM Incorporated
发明人： Mazhareddin Taghivand , Yashar Rajavi , Alireza Khalili
IPC分类号： H03L5/00 , H03K5/08 , H03H11/24 , H03H1/02
摘要： Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor having a gate, a source connected with a first node of the circuit, and a drain connected with a second node of the circuit. The circuit may also include a voltage-limiting device connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.

7. 发明申请

US20180198432A1 Parallel RC Circuit Equalizers 审中-公开
公开(公告)号：US20180198432A1
公开(公告)日：2018-07-12
申请号：US15864176
申请日：2018-01-08
申请人： AVX Corporation
发明人： Gheorghe Korony
IPC分类号： H03H7/06 , H03H1/02 , H04B3/04
CPC分类号： H03H7/06 , H03H1/02 , H04B3/04
摘要： Disclosed are apparatus and methodology for increasing the resonance frequency and useful frequency range of surface mount RC equalizer devices. The presently disclosed subject matter provides improved operational characteristics of generally known such RC equalizer devices by implementing a reverse geometry that relocates the internal termination points, as well as external termination points for such devices, along lateral portions of the assembled device. Such reverse geometry achieves improvements by providing a reduction of the equivalent series inductance (ESL) to provide the increased resonance frequency and useful frequency range.

8. 发明授权

US09673774B2 Apparatus and methods for high voltage variable capacitor arrays with body biasing resistors 有权
公开(公告)号：US09673774B2
公开(公告)日：2017-06-06
申请号：US14705381
申请日：2015-05-06
申请人： TDK Corporation
发明人： Anuj Madan , Dev V. Gupta , Zhiguo Lai
IPC分类号： H03H7/06 , H01G7/00 , H01L27/08 , H03H7/01 , H03H1/02 , H03H11/04 , H03H11/28 , H03H5/12 , H03H1/00
CPC分类号： H03H7/06 , H01G7/00 , H01L27/0805 , H03H1/02 , H03H5/12 , H03H7/0138 , H03H7/0153 , H03H7/0161 , H03H7/17 , H03H11/04 , H03H11/28 , H03H2001/0014 , H03H2001/0064
摘要： Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

9. 发明申请

US20160112024A1 INDUCTOR CIRCUIT INTEGRATED WITH RC CIRCUIT 审中-公开
标题翻译：电感电路与RC电路集成
公开(公告)号：US20160112024A1
公开(公告)日：2016-04-21
申请号：US14516514
申请日：2014-10-16
申请人： HON HAI PRECISION INDUSTRY CO., LTD.
发明人： CHI-KUNG SU , JYUN-DA LIAO , WEI-LUNG HUANG
IPC分类号： H03H1/02 , H01F27/29
CPC分类号： H01F27/29 , H01F17/00 , H01F27/292 , H03H5/02
摘要： An inductor circuit includes an inductor and an RC circuit. The RC circuit includes a resistor and a capacitor. The resistor and the capacitor are coupled in series. A first terminal of the inductor is coupled to the resistor through a first contact. The resistor is coupled to the capacitor through a second contact. The capacitor is coupled to a second terminal of the inductor through a third contact.
摘要翻译：电感电路包括电感和RC电路。 RC电路包括一个电阻和一个电容。电阻器和电容器串联耦合。电感器的第一端子通过第一触点耦合到电阻器。电阻器通过第二接触耦合到电容器。电容器通过第三触点耦合到电感器的第二端子。

10. 发明授权

US07719380B2 AC coupling circuit 失效
标题翻译：交流耦合电路
公开(公告)号：US07719380B2
公开(公告)日：2010-05-18
申请号：US10920592
申请日：2004-08-17
申请人： Jeffry D. Yetter , Dacheng Zhou
发明人： Jeffry D. Yetter , Dacheng Zhou
IPC分类号： H03H1/02 , H01P5/02
CPC分类号： H04B3/00
摘要： An AC coupling circuit is disclosed herein. An embodiment of the circuit comprises a first differential input and a second differential input. A first resistor is connected between the first differential input and the second differential input. A first capacitor is connected between the first differential input and a first differential output. A second capacitor is connected between the second differential input and a second differential output. A second resistor is connected between the first differential output and a node. A third resistor is connected between the second differential output and the node. A first potential is applied to the node.
摘要翻译：本文公开了一种AC耦合电路。电路的实施例包括第一差分输入和第二差分输入。第一电阻器连接在第一差分输入和第二差分输入之间。第一电容器连接在第一差分输入和第一差分输出之间。第二电容器连接在第二差分输入和第二差分输出之间。第二电阻连接在第一差分输出和节点之间。第三个电阻连接在第二个差分输出和节点之间。第一个潜力被应用于节点。

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