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1. 发明授权

US11309900B2 Monitor circuitry for power management and transistor aging tracking 有权
公开(公告)号：US11309900B2
公开(公告)日：2022-04-19
申请号：US16913933
申请日：2020-06-26
申请人： Intel Corporation
发明人： Kuan-Yueh Shen , Nasser A. Kurd , John Fallin
IPC分类号： H03L7/099 , H03L7/089 , H01R13/66 , H03L7/189
摘要： Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.

2. 发明授权

US11139817B1 Voltage-controlled oscillator calibration 有权
公开(公告)号：US11139817B1
公开(公告)日：2021-10-05
申请号：US16855828
申请日：2020-04-22
申请人： Apple Inc.
发明人： Long Kong , Simone Gambini , Cristian Marcu , Nachum M. Kanovsky
IPC分类号： H03L7/091 , H03L7/099 , H03L7/189 , H03L7/10
摘要： A computer system may periodically calibrate an oscillator subsystem, which includes a voltage-controlled oscillator circuit configured to generate an oscillator signal using code signal. In response to activation of a calibration mode, an iterative calibration operation may be performed on the voltage-controlled oscillator circuit. In some cases, performing a given iteration of the calibration operation includes determining a value of the code signal using a number of pulses in the oscillator signal sampled during a particular time period, along with previous values of the code signal and a slope of an error function associated with the difference between a desired frequency and a current frequency of the oscillator signal. In other cases, iterations may employ variable sampling times with error handling, in order to decrease the duration of the calibration operation while maintaining a target accuracy.

3. 发明授权

US10804910B2 Circuit device, oscillator, electronic apparatus and moving object 有权
公开(公告)号：US10804910B2
公开(公告)日：2020-10-13
申请号：US16715482
申请日：2019-12-16
申请人： SEIKO EPSON CORPORATION
发明人： Hideki Sato
IPC分类号： H03L7/099 , H03L1/02 , H03L7/089 , H03L7/00 , H03L7/189 , H03L7/197 , H04B1/707 , H03M7/36 , H03B5/32
摘要： A circuit device includes a phase comparison circuit that performs phase comparison between a reference clock signal and a feedback clock signal, a control voltage generation circuit that generates a control voltage, a voltage controlled oscillation circuit that generates a clock signal, a dividing circuit that divides the clock signal and outputs the feedback clock signal, a processing circuit that sets a division ratio of the dividing circuit, a first register in which slope information of a waveform signal for spreading the frequency of the clock signal is set, and a second register in which amplitude information of the waveform signal is set. The processing circuit generates a waveform signal value based on the slope information and the amplitude information set in the first and second registers, and outputs division ratio data based on the waveform signal value and the division ratio setting value to the dividing circuit.

4. 发明授权

US10790838B1 Method and apparatus to perform dynamic frequency scaling while a phase-locked loop operates in a closed loop 有权
公开(公告)号：US10790838B1
公开(公告)日：2020-09-29
申请号：US16412165
申请日：2019-05-14
申请人： Intel Corporation
发明人： Praveen Mosalikanti , Vaughn J. Grossnickle , Syed Feruz Syed Farooq , Mark Neidengard , Nasser A. Kurd
IPC分类号： H03L7/189 , H03L7/099 , H03L7/197 , H03L7/085
摘要： Dynamic voltage frequency scaling to transition to a target clock frequency and associated target voltage is provided. Dynamic voltage frequency scaling to a different clock frequency is performed by gradually changing the clock frequency using discrete variable-size steps, while dynamically switching to faster or slower reference clock frequencies as appropriate to harmonize the frequency trajectory with system requirements.

5. 发明授权

US09571077B1 Dynamic update technique for phase interpolator device and method therefor 有权
标题翻译：相位插值器器件的动态更新技术及其方法
公开(公告)号：US09571077B1
公开(公告)日：2017-02-14
申请号：US14798340
申请日：2015-07-13
申请人： Rambus Inc.
发明人： Cosmin Iorga , James L. Gorecki
IPC分类号： H03H11/16 , H03K5/13 , H03K5/135 , H03L7/189 , H03L7/191
CPC分类号： H03K5/131 , H03K5/135
摘要： A method and device for dynamically updating a phase interpolator circuit module using a phase update circuit module. The method can include interpolating a set of input clock phases based on a phase interpolator code input and sequentially updating the rising edge generator and falling edge generator starting from a synchronizer update signal. The dynamic sequential update involves disabling a rising edge ramp signal while updating a rising edge interpolator and generating old clock out falling edge according to an old phase interpolator code input, disabling a falling edge ramp signal while updating a falling edge interpolator, enabling the rising edge ramp signal and generating a new clock out rising edge according to a new phase interpolator code input, and enabling the falling edge ramp signal and generating a new clock out falling edge according to the new phase interpolator code input.
摘要翻译：一种使用相位更新电路模块动态更新相位插值器电路模块的方法和装置。该方法可以包括基于相位内插器代码输入来内插一组输入时钟相位，并且从同步器更新信号开始顺序更新上升沿发生器和下降沿发生器。动态顺序更新包括在更新上升沿内插器时禁止上升沿斜坡信号，并根据旧相位内插器代码输入产生旧时钟下降沿，在更新下降沿内插器时禁止下降沿斜坡信号，使上升沿根据新的相位内插器代码输入，产生新的时钟输出上升沿，并根据新的相位内插器代码输入使能下降沿斜坡信号并产生新的时钟下降沿。

6. 发明授权

US09490831B2 Time-to-digital converter using stochastic phase interpolation 有权
标题翻译：使用随机相位插值的时间 - 数字转换器
公开(公告)号：US09490831B2
公开(公告)日：2016-11-08
申请号：US14817727
申请日：2015-08-04
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sung-Jin Kim , Jihyun Kim , Taeik Kim
IPC分类号： H03L7/06 , H03L7/189 , G04F10/00
CPC分类号： H03L7/189 , G04F10/005 , H03L7/085 , H03L7/18
摘要： Provided is a time-to-digital converter. The time-to-digital converter includes several delay circuits, an adder configured to count outputs of the delay circuits, and a least significant bit (LSB) truncation circuit configured to truncate a predetermined number of LSBs from a result output by the adder. The time-to-digital converter is configured to determine a time interval between a start signal and a stop signal within one cycle of a clock having a predetermined period.
摘要翻译：提供了一个时间 - 数字转换器。时间数字转换器包括若干延迟电路，被配置为对延迟电路的输出进行计数的加法器和被配置为从加法器输出的结果中截断预定数量的LSB的最低有效位（LSB）截断电路。时间数字转换器被配置为在具有预定周期的时钟的一个周期内确定起始信号和停止信号之间的时间间隔。

7. 发明授权

US06914489B2 Voltage-controlled oscillator presetting circuit 有权
标题翻译：压控振荡器预置电路
公开(公告)号：US06914489B2
公开(公告)日：2005-07-05
申请号：US10259012
申请日：2002-09-26
申请人： Olivier Charlon
发明人： Olivier Charlon
IPC分类号： H03L7/189 , H03L7/00
CPC分类号： H03L7/189
摘要： A circuit comprises a frequency synthesizing circuit with a voltage-controlled oscillator whose frequency is preset to a preset value. The voltage-controlled oscillator generates an oscillating signal in response to an input voltage. The frequency synthesizing circuit is configured to operate in a locked loop mode under control of an error signal representative of a phase frequency differential between the divided oscillating signal and a reference signal. A digital processing unit can disable the frequency synthesizing circuit to operate in phase locked loop mode. Once the synthesizing circuit is disabled, the digital processing unit determines a first and a second frequency of the oscillating signal in response to respective first and second loop filter input voltage values. The unit further generates a control value from the two frequencies, the frequency divider dividing ratio and the reference signal. The circuit further comprises a digital to analog converter configured to preset the loop filter input voltage to a preset value in response to the control value. Once the voltage controlled oscillator output oscillates at the corresponding input preset value, the digital processing unit disables the digital to analog converter and enables the frequency synthesizing to operate in phase locked loop mode.
摘要翻译：电路包括具有频率预设为预设值的压控振荡器的频率合成电路。压控振荡器响应于输入电压产生振荡信号。频率合成电路被配置为在表示分频振荡信号与参考信号之间的相位差的误差信号的控制下在锁定环路模式下工作。数字处理单元可以禁止频率合成电路在锁相环模式下工作。一旦合成电路被禁用，数字处理单元响应于相应的第一和第二环路滤波器输入电压值来确定振荡信号的第一和第二频率。该单元进一步从两个频率，分频器分频比和参考信号产生控制值。电路还包括数模转换器，其被配置为响应于控制值将环路滤波器输入电压预设为预设值。一旦压控振荡器输出以相应的输入预置值振荡，数字处理单元禁用数模转换器，并使频率合成能够在锁相环模式下工作。

8. 发明授权

US6091943A Combining oscillator with a phase-indexed control circuit for a radio receiver 失效
标题翻译：将振荡器与无线电接收机的相位索引控制电路相结合
公开(公告)号：US6091943A
公开(公告)日：2000-07-18
申请号：US91372
申请日：1998-06-17
申请人： Detlev Nyenhuis
发明人： Detlev Nyenhuis
IPC分类号： H03L7/093 , H03J1/00 , H03L7/107 , H03L7/189 , H04B1/06
CPC分类号： H03J1/0066 , H03L7/189
摘要： A mixer oscillator with a phase-locked loop control loop for a radio receiver is described in which a digital loop filter in the control loop includes which an integrator for digital output signals of a phase discriminator which is preprogrammed frequency jumps. The digital loop filter includes two switchable integrators for optional alternate switching of alternate test frequencies.
摘要翻译： PCT No.PCT / DK96 / 00517 Sec。 371日期1998年6月17日第 102（e）1998年6月17日PCT 1996年12月9日PCT PCT。第WO97 / 23957号公报日期1997年7月3日描述了一种用于无线电接收机的具有锁相环控制回路的混频器振荡器，其中控制回路中的数字环路滤波器包括用于预编程频率跳变的相位鉴别器的数字输出信号的积分器。数字环路滤波器包括两个可切换的积分器，用于替代测试频率的可选替代切换。

9. 发明授权

US6091281A High precision reference voltage generator 失效
标题翻译：高精度参考电压发生器
公开(公告)号：US6091281A
公开(公告)日：2000-07-18
申请号：US35406
申请日：1998-03-05
申请人： Haruo Yoshida
发明人： Haruo Yoshida
IPC分类号： G01R1/28 , G01R31/28 , G05F1/56 , H03L7/06 , H03L7/093 , H03L7/10 , H03L7/189 , H01J19/82
CPC分类号： H03L7/10 , G01R31/2841 , H03L7/093 , H03L7/189
摘要： A reference voltage generator includes a voltage controlled oscillator which has fixed and accurate relationship between a frequency of an oscillation signal and a voltage supplied thereto, a reference frequency oscillator for generating a reference frequency signal of high accuracy and stability, a phase comparator for detecting a phase difference between the oscillation signal of the voltage controlled oscillator and the reference frequency signal, a low pass filter for smoothing a detection signal from the phase comparator, a gain adjust circuit for amplifying a signal from the low pass filter, a voltage adder for providing a sum of voltages from the gain adjust circuit and an offset voltage to the voltage controlled oscillator, and a phase clock loop formed by the phase comparator, low pass filter, gain adjust circuit and voltage adder to null the phase difference by regulating a control voltage applied to the voltage controlled oscillator.
摘要翻译：参考电压发生器包括一个压控振荡器，其在振荡信号的频率和提供给它的电压之间具有固定和精确的关系，用于产生高精度和稳定性的参考频率信号的参考频率振荡器，用于检测振荡信号的相位比较器压控振荡器的振荡信号与参考频率信号之间的相位差，用于平滑来自相位比较器的检测信号的低通滤波器，用于放大来自低通滤波器的信号的增益调整电路，用于提供来自增益调整电路的电压和压控振荡器的偏移电压之和，以及由相位比较器，低通滤波器，增益调整电路和电压加法器形成的相位时钟环，通过调节控制电压施加到压控振荡器。

10. 发明授权

US5757238A Fast locking variable frequency phase-locked loop 失效
标题翻译：快速锁定可变频率锁相环
公开(公告)号：US5757238A
公开(公告)日：1998-05-26
申请号：US699296
申请日：1996-08-19
申请人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
发明人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
IPC分类号： H03L7/089 , H03L7/099 , H03L7/189 , H03L7/18
CPC分类号： H03L7/0995 , H03L7/089 , H03L7/189 , H03L2207/06
摘要： According to the preferred embodiment of the present invention, a phase-locked loop is provided that overcomes the limitations of the prior art by facilitating fast locking on transition to a different output frequency. The phase-locked loop comprises an oscillator that provides a phase-locked loop output signal at various selected frequencies; a feedback divider; a phase comparator; a memory storage mechanism for storing phase-locked loop control information corresponding to selected output frequencies; and a digital circuit mechanism that receives the control information from the memory storage mechanism on transition to a different output frequency. The control information includes a digital counter value corresponding to the last recorded phase difference of the output signal at the different output frequency. On transition, this information is loaded directly to the digital circuit mechanism, reducing the need and time required for the phase comparator operation to drive the PLL to lock. Thus, the phase-locked loop can quickly achieve phase lock at the different operating frequency.
摘要翻译：根据本发明的优选实施例，提供了一种锁相环，其克服了现有技术的限制，通过促进快速锁定转换到不同的输出频率。锁相环包括以各种选定频率提供锁相环输出信号的振荡器; 反馈分配器相位比较器用于存储对应于所选择的输出频率的锁相环控制信息的存储器存储机构; 以及数字电路机构，其在转换到不同的输出频率时从存储器存储机构接收控制信息。控制信息包括对应于不同输出频率处的输出信号的最后记录的相位差的数字计数器值。在转换时，该信息直接加载到数字电路机制，减少了相位比较器操作驱动PLL锁定所需的时间和时间。因此，锁相环可以在不同的工作频率下快速实现锁相。

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