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1. 发明公开

US20240283409A1 SLOPE-TEMPERATURE DRIFT CALIBRATION OF A SIGNAL STRENGTH DETECTOR 审中-公开
公开(公告)号：US20240283409A1
公开(公告)日：2024-08-22
申请号：US18581919
申请日：2024-02-20
申请人： Analog Devices, Inc.
发明人： Petrus M. Stroet , Daniel J. Linebarger , John P. Myers , Michael Hendrikus Laurentius Kouwenhoven
IPC分类号： H03F1/30 , H03F3/45 , H03M1/72
CPC分类号： H03F1/302 , H03F3/45085 , H03M1/72 , H03F2200/261 , H03F2200/462
摘要： A device may include an analog signal chain that adjusts a slope-temperature drift of the signal-strength detector by adjusting a delta proportional to absolute temperature of the analog signal chain. The device may further include an intercept-temperature drift input to receive an intercept-temperature drift value. Additionally, the device may include a reference current generator that generates a reference current based at least in part on the intercept-temperature drift value.

2. 发明授权

US11774928B2 Interventional control method based on computer control system and interventional computer control system 有权
公开(公告)号：US11774928B2
公开(公告)日：2023-10-03
申请号：US16959946
申请日：2018-10-26
申请人： Puyang Baifu Reide Petroleum Science and Technology Company Limited
发明人： Gang Zhao , Chen Chen , Chun Yu , Yulong Xia , Yingdong Zhang
IPC分类号： H03M1/00 , G05B15/02 , H03M1/12 , H03M1/72
CPC分类号： G05B15/02 , H03M1/001 , H03M1/12 , H03M1/72
摘要： An interventional control method based on a computer control system. An interventional control system is designed on the basis of an original computer control system; the analog-to-digital conversion unit of the interventional control system receives a signal from the data acquisition module of the original computer control system and said signal is processed by a control processing unit according to a built-in program; then a digital-to-analog conversion unit performs digital-to-analog conversion on the signal output by the control processing unit and then outputs a signal obtained after the digital-to-analog conversion to the analog-to-digital conversion unit of the original computer control system. According to the interventional computer control system, on the basis of an original computer control system, the analog-to-digital conversion unit of the interventional control system receives a signal output from the data acquisition module of the original computer control system and control processing is performed on said output signal; then the digital-to-analog conversion unit of the interventional control system outputs a signal to the analog-to-digital conversion unit of the original computer control system. The function upgrade of an original computer control system is implemented without changing the operating program of the original computer control system.

3. 发明授权

US11697021B2 Current generation architecture for an implantable stimulator device to promote current steering between electrodes 有权
公开(公告)号：US11697021B2
公开(公告)日：2023-07-11
申请号：US17140850
申请日：2021-01-04
申请人： Boston Scientific Neuromodulation Corporation
发明人： Pujitha Weerakoon , David M. Wagenbach , Philip L. Weiss , Goran N. Marnfeldt
IPC分类号： A61N1/36 , A61N1/02 , H03M1/74 , H03M1/72
CPC分类号： A61N1/36157 , A61N1/025 , A61N1/36125 , H03M1/72 , H03M1/745
摘要： An implantable pulse generator (IPG) is disclosed having an improved ability to steer anodic and cathodic currents between the IPG's electrodes. Each electrode node has at least one PDAC/NDAC pair to source/sink or sink/source a stimulation current to an associated electrode node. Each PDAC and NDAC receives a current with a magnitude indicative of a total anodic and cathodic current, and data indicative of a percentage of that total that each PDAC and NDAC will produce in the patient's tissue at any given time, which activates a number of branches in each PDAC or NDAC. Each PDAC and NDAC may also receive one or more resolution control signals specifying an increment by which the stimulation current may be adjusted at each electrode. The current received by each PDAC and NDAC is generated by a master DAC, and is preferably distributed to the PDACs and NDACs by distribution circuitry.

4. 发明授权

US11438006B2 Method to operate an optical sensor arrangement with improved conversion accuracy and optical sensor arrangement 有权
公开(公告)号：US11438006B2
公开(公告)日：2022-09-06
申请号：US16955343
申请日：2018-12-18
申请人： ams International AG
发明人： Louis Albert Williams, III , Yong Han
IPC分类号： H03M1/72 , H03M1/52 , G01J1/46 , H03M1/46 , H04N5/3745 , H04N5/378 , G01J1/44
摘要： An optical sensor arrangement comprises a photodiode and a converter arrangement including an integration amplifier, a comparator amplifier, an integration capacitor and a result register. During a precharge phase the result register is set to a starting value. During an integration phase a current is sampled through the photodiode to update the result register in response to down charges applied to an input of the integration amplifier. During a residue phase the result register is updated in dependence on the charge remaining on the integration capacitor. Measuring the residual charge increases resolution and accuracy of the converter.

5. 发明授权

US10912942B2 Current generation architecture for an implantable stimulator device to promote current steering between electrodes 有权
公开(公告)号：US10912942B2
公开(公告)日：2021-02-09
申请号：US16131809
申请日：2018-09-14
申请人： Boston Scientific Neuromodulation Corporation
发明人： Pujitha Weerakoon , David M. Wagenbach , Philip L. Weiss , Goran N. Marnfeldt
IPC分类号： A61N1/36 , A61N1/08 , A61N1/02 , H03M1/74 , H03M1/72
摘要： An implantable pulse generator (IPG) is disclosed having an improved ability to steer anodic and cathodic currents between the IPG's electrodes. Each electrode node has at least one PDAC/NDAC pair to source/sink or sink/source a stimulation current to an associated electrode node. Each PDAC and NDAC receives a current with a magnitude indicative of a total anodic and cathodic current, and data indicative of a percentage of that total that each PDAC and NDAC will produce in the patient's tissue at any given time, which activates a number of branches in each PDAC or NDAC. Each PDAC and NDAC may also receive one or more resolution control signals specifying an increment by which the stimulation current may be adjusted at each electrode. The current received by each PDAC and NDAC is generated by a master DAC, and is preferably distributed to the PDACs and NDACs by distribution circuitry.

6. 发明授权

US10044366B2 Non-linear gamma compensation current mode digital-analog convertor and display device including the same 有权
公开(公告)号：US10044366B2
公开(公告)日：2018-08-07
申请号：US14218952
申请日：2014-03-18
申请人： Samsung Display Co., Ltd. , Korea Advanced Institute of Science and Technology
发明人： Oh Jo Kwon , Kyung Youl Min , Choong Sun Shin , Hee Sun Ahn , Hyun Sik Kim , Jun Suk Bang , Gyu Hyeong Cho
IPC分类号： G09G3/32 , H03M1/72 , G09G3/3275
摘要： A non-linear gamma compensation current mode digital-analog converter includes: a first digital-analog converter block configured to: receive a digital signal, a first reference voltage, and a gamma adjustment voltage, and provide a reference current to a ground, wherein a first current flowing to a first current output terminal is determined according to the digital signal and the gamma adjustment voltage; and a second digital-analog converter block configured to: receive the digital signal, a second reference voltage, and a ground voltage, and provide the first current to the first digital-analog converter, wherein a second current flowing to a second current output terminal is determined according to the digital signal and the first current.

7. 发明申请

US20170085399A1 PULSED DECISION FEEDBACK EQUALIZATION CIRCUIT 审中-公开
公开(公告)号：US20170085399A1
公开(公告)日：2017-03-23
申请号：US14863300
申请日：2015-09-23
申请人： INTEL CORPORATION
发明人： Salman Latif , Ravindran Mohanavelu , Sitaraman V. Iyer
IPC分类号： H04L25/03 , H03M1/72 , H03M1/06 , H04L27/01
CPC分类号： H04L25/03146 , H03M1/72 , H04L25/03006
摘要： Embodiments include a pulsed decision feedback equalization (DFE) circuit. The DFE circuit may include a current integrating summer (CIS) circuit that passes one or more data signals on respective data nodes based on an input data signal and a clock signal. The DFE circuit may further include a correction circuit, such as a current digital-to-analog converter (IDAC) circuit, that may provide a correction circuit to a data node based on a prior bit of the input data signal. The correction circuit may provide a conductive path between a current source of the correction circuit and the data node for a time period that is less than the unit interval (UI) of the clock signal and/or data signal. The DFE circuit may include a plurality of correction circuits to provide respective correction signals based on different prior bits of the input data signal. Other embodiments may be described and claimed.

8. 发明授权

US08872686B2 Low glitch current digital-to-analog converter 有权
标题翻译：低毛刺电流数模转换器
公开(公告)号：US08872686B2
公开(公告)日：2014-10-28
申请号：US13858445
申请日：2013-04-08
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Kuo-Yu Chou , Wei Lun Tao , Shang-Fu Yeh , Yi-Che Chen , Calvin Yi-Ping Chao
IPC分类号： H03M1/66 , H03M1/72
CPC分类号： H03M1/0863 , H03M1/685 , H03M1/747
摘要： The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed.
摘要翻译：本公开涉及一种使包含相同当前单位单元的阵列的当前数模转换器（DAC）内的瞬态毛刺最小化的方法和架构。当前DAC配置有用于当前单位单元的偶数和奇数行的单独列解码器，从而允许独立控制相邻行。偶数行和奇数行列解码器还包括具有耦合定时编码的热解码器，其建立相邻行对之间的协同作用。由于活动行中的当前单位单元通过第一列解码器的计数而在整个行上被激活，所以与活动行相邻的下一行内的当前单位单元通过向下计数而返回到活动行的初始状态第二列解码器。还公开了其它装置和方法。

9. 发明授权

US07783795B2 Serial communication circuit and A/D conversion system having the same 有权
标题翻译：串行通信电路和A / D转换系统具有相同的功能
公开(公告)号：US07783795B2
公开(公告)日：2010-08-24
申请号：US11581443
申请日：2006-10-17
申请人： Takuya Honda
发明人： Takuya Honda
IPC分类号： G06F13/00 , G06F13/12 , H03M1/00 , H03M1/72
CPC分类号： G06F13/4291
摘要： A serial communication circuit for performing full duplex serial communication with a microcomputer includes a counter and a timer. The counter is incremented by each pulse of a serial clock signal output from the microcomputer. When the counter reaches the number of bits of serial data output from the microcomputer, the counter outputs a load signal to a receiving register. The timer starts to count after the counter outputs the receiving load signal for the first time and continues to count during the serial communication. The timer expires at a predetermined time interval. Each time the timer expires, the timer outputs a timer signal. In response to the timer signal, a synchronous signal is output to the microcomputer, the counter is cleared to zero, and data to be output to the microcomputer is loaded into a sending register.
摘要翻译：用于与微计算机执行全双工串行通信的串行通信电路包括计数器和定时器。计数器由微机输出的串行时钟信号的每个脉冲递增。当计数器达到从微型计算机输出的串行数据的位数时，计数器将一个负载信号输出到接收寄存器。计数器第一次输出接收负载信号后，定时器开始计数，并在串行通信期间继续计数。定时器以预定的时间间隔过期。每次定时器超时，定时器输出定时器信号。响应于定时器信号，将同步信号输出到微计算机，计数器清零，将要输出到微计算机的数据加载到发送寄存器中。

10. 发明申请

US20100156689A1 A-D CONVERT APPARATUS, D-A CONVERT APPARATUS AND ADJUSTMENT METHOD 失效
标题翻译： A-D转换装置，D-A转换装置和调整方法
公开(公告)号：US20100156689A1
公开(公告)日：2010-06-24
申请号：US12342078
申请日：2008-12-23
申请人： YASUHIDE KURAMOCHI , AKIRA MATSUZAWA
发明人： YASUHIDE KURAMOCHI , AKIRA MATSUZAWA
IPC分类号： H03M1/12 , H03M1/72
CPC分类号： H03M1/1061 , H03M1/0643 , H03M1/468 , H03M1/68 , H03M1/78 , H03M1/804
摘要： An A/D conversion device including a first A/D conversion section and a second A/D conversion section that each include a D/A converter that has a plurality of bit capacitors corresponding to bits of input data, a comparing section that compares a reference voltage with a difference voltage obtained by subtracting an analog input voltage from an output voltage of the D/A converter, and a control section that detects a data value of the input data at which the difference voltage is substantially the same as the reference voltage and outputs the data value as digital data according to the input voltage, and an adjusting section that serially connects the bit capacitors of the D/A converter of the first A/D conversion section and the bit capacitors of the D/A converter of the second A/D conversion section that correspond to the same bits, and adjusts a capacity of at least one of the bit capacitors so that a voltage between the two bit capacitors approaches a middle point of voltages of the two bit capacitors.
摘要翻译：一种A / D转换装置，包括第一A / D转换部分和第二A / D转换部分，每个A / D转换部分包括具有对应于输入数据的位的多个位电容器的D / A转换器，比较部分具有通过从D / A转换器的输出电压减去模拟输入电压而获得的差分电压的参考电压;以及控制部，其检测差分电压与基准电压基本相同的输入数据的数据值并且根据输入电压输出数据值作为数字数据;以及调整部，其将第一A / D转换部的D / A转换器的位电容串行连接到D / A转换部的位电容器第二A / D转换部分，其对应于相同的位，并且调整至少一个位电容器的容量，使得两个位电容器之间的电压接近电压的中点他两位电容。

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