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1. 发明授权

US06836520B1 Method and apparatus for establishing synchronization with a synchronization signal 有权
标题翻译：用于与同步信号建立同步的方法和装置
公开(公告)号：US06836520B1
公开(公告)日：2004-12-28
申请号：US09709727
申请日：2000-11-10
申请人： Weizhong Chen , Leo Dehner
发明人： Weizhong Chen , Leo Dehner
IPC分类号： H04L700
CPC分类号： H04L27/0012 , H04L7/042 , H04L7/06 , H04L2027/0034
摘要： A synchronization signal includes a plurality of predetermined synchronization symbols shaped by a predetermined symbol pulse. A receiver (100) receives (202) a signal including the synchronization signal, and a processor (106)determines (204) a first plurality of cross-correlations between the predetermined symbol pulse and the received signal. The processor calculates (206) a plurality of sums of products of the plurality of predetermined synchronization symbols and a predetermined subset of the first plurality of cross-correlations. The plurality of sums are mathematically equivalent to a second plurality of cross-correlations between the synchronization signal and the received signal. The processor locates (208) a peak of the plurality of sums to establish receiver synchronization.
摘要翻译：同步信号包括由预定符号脉冲整形的多个预定同步符号。接收器（100）接收（202）包括同步信号的信号，并且处理器（106）确定（204）预定符号脉冲与接收信号之间的第一多个互相关。处理器计算（206）多个预定同步符号的乘积和与第一多个互相关的预定子集的多个和。多个和在数学上等同于同步信号和接收信号之间的第二多个互相关。处理器定位（208）多个和的峰值以建立接收机同步。

2. 发明授权

US06834040B2 Measurement synchronization method for voice over packet communication systems 有权
标题翻译：语音分组通信系统的测量同步方法
公开(公告)号：US06834040B2
公开(公告)日：2004-12-21
申请号：US09784428
申请日：2001-02-15
申请人： Jeffrey Tomberlin
发明人： Jeffrey Tomberlin
IPC分类号： H04L700
CPC分类号： H04L43/50 , H04J3/0632
摘要： A method for synchronizing a measurement in a communication system. Recent developments in communication systems have resulted in combining the traffic historically carried separately by telephone and data networks. The service provided by such systems is referred to as Voice over Packet (VoP) with the more popular version using the Internet Protocol (IP) commonly referred to as Voice over IP (VoIP). VoP technologies have made maintaining voice quality at high levels more complex by compressing the voice signal and transmitting it in discrete packets. With voice traffic there is the need for timely packet delivery, often in networks that were not originally designed for these conditions. Digitizing analog voice signals often affects voice clarity. Objective tests for voice quality are available but are difficult to synchronize between stations. In methods disclosed pseudo-random analogue signals which emulate white noise are created and used as synchronization signals which enable this synchronization more precisely than previous methods. These signals are relatively unaffected by the codecs commonly used for voice and data compression.
摘要翻译：一种在通信系统中同步测量的方法。通信系统的最新发展导致了电话和数据网络单独携带的流量合并。由这种系统提供的服务被称为使用通常被称为IP语音（VoIP）的因特网协议（IP）的较流行版本的语音分组（VoP）。 VoP技术通过压缩语音信号并以离散数据包传输，使语音质量保持在更高的水平。通过语音流量，需要及时提供数据包传输，通常不是最初设计用于这些条件的网络。数字化模拟语音信号通常会影响语音清晰度。语音质量的客观测试可用，但是站点之间难以同步。在公开的方法中，产生模拟白噪声的伪随机模拟信号，并将其用作同步信号，这使得该同步比先前的方法更精确。这些信号相对不受通常用于语音和数据压缩的编解码器的影响。

3. 发明授权

US06829315B1 Alignment of parallel data channels using header detection signaling 有权
标题翻译：使用标题检测信令对并行数据信道进行比对
公开(公告)号：US06829315B1
公开(公告)日：2004-12-07
申请号：US09487139
申请日：2000-01-19
申请人： Brian S. Cruikshank
发明人： Brian S. Cruikshank
IPC分类号： H04L700
CPC分类号： H04J3/0605 , H04L25/14
摘要： A data communication circuit includes a decoder and an alignment buffer. The decoder receives and decodes parallel (N) bit channels into parallel (M+X) bit channels with signaling bits that indicate headers in the parallel (M+X) bit channels. The decoder transfers the parallel (M+X) bit channels to the alignment buffer. The alignment buffer recovers and aligns parallel (M) bit channels using the signaling bits. The alignment buffer generates a clock selection signal using the signaling bits. The alignment buffer transfers the aligned parallel (M) bit channels and the clock selection signal. The alignment buffer can have a length that is a multiple of a frame length for the (M) bit parallel channels.
摘要翻译：数据通信电路包括解码器和对准缓冲器。解码器将并行（N）比特信道接收并解码为并行（M + X）比特信道，信令比特指示并行（M + X）比特信道中的报头。解码器将并行（M + X）位通道传送到对准缓冲器。对准缓冲器使用信令位恢复并对齐并行（M）位通道。对准缓冲器使用信令位产生时钟选择信号。对准缓冲器传送对准的并行（M）位通道和时钟选择信号。对准缓冲器可以具有为（M）位并行通道的帧长度的倍数的长度。

4. 发明授权

US06819727B1 Method and device for the numeric control of the buffer and of a phase-locked loop for asynchronous networks 失效
标题翻译：用于数字控制缓冲器和异步网络的锁相环的方法和装置
公开(公告)号：US06819727B1
公开(公告)日：2004-11-16
申请号：US09340204
申请日：1999-06-28
申请人： Silvio Cucchi , Daniele Meli
发明人： Silvio Cucchi , Daniele Meli
IPC分类号： H04L700
CPC分类号： H04L12/5601 , H04J3/0632 , H04L2012/5616 , H04L2012/5674 , H04L2012/5681 , H04Q11/0478
摘要： A method and device is described for the numeric control of buffer and phase-locked loop for the recovery of the synchronism and the optimized management over communication networks having a high jitter like, e.g., networks in which the ATM mode (Asynchronous Transfer Mode), is used. The innovation resides in the buffer management which is carried out according to the input phase statistic characteristics (in part known a priori and in part measured by the system) as well as to its measured value (which is equivalent to the buffer filling level) thus introducing the concept of statistic pointers. This allows an optimal management thereof and also permits to control the buffer overflow and underflow probabilities. Moreover, by associating the present device with another phase locked device, it is possible to obtain a high frequency stability of the reconstructed sync signal, attenuating at a large extent the jitter introduced by the network, even at a very low frequency.
摘要翻译：描述了用于恢复同步的缓冲器和锁相环的数字控制的方法和装置，以及具有高抖动的通信网络的优化管理，例如，其中ATM模式（异步传输模式），用来。该创新在于根据输入相位统计特性（部分已知先决且部分由系统测量）进行的缓冲器管理以及其测量值（相当于缓冲器填充水平），因此介绍统计指针的概念。这允许其最佳管理，并且还允许控制缓冲器溢出和下溢概率。此外，通过将本装置与另一个锁相装置相关联，可以获得重建的同步信号的高频稳定性，在很大程度上衰减网络引入的抖动，即使在非常低的频率下也是如此。

5. 发明授权

US06810484B2 Device and method for clock synchronization through extraction of data at frequency distinct from data rate of USB interface 有权
标题翻译：通过提取与USB接口的数据速率不同的频率的数据进行时钟同步的装置和方法
公开(公告)号：US06810484B2
公开(公告)日：2004-10-26
申请号：US09797131
申请日：2001-03-01
申请人： Ravikumar Govindaraman
发明人： Ravikumar Govindaraman
IPC分类号： H04L700
CPC分类号： H04L7/02 , G06F13/4059 , H04L7/04
摘要： The device and method that receives a signal from a first interface operating at a data rate. An extraction component extracts information from the signal to produce an information signal having a frequency distinct from the data rate of the first interface. A first receive clock component receives a first clock signal that has a frequency equal to a frequency of a second interface. A synchronizer component synchronizes the information signal through utilization of the first clock signal to the frequency of the second interface.
摘要翻译：从以数据速率操作的第一接口接收信号的设备和方法。提取组件从信号中提取信息以产生具有与第一接口的数据速率不同的频率的信息信号。第一接收时钟分量接收具有等于第二接口的频率的频率的第一时钟信号。同步器部件通过利用第一时钟信号与第二接口的频率同步信息信号。

6. 发明授权

US06802019B1 Method and system for synchronizing data 有权
标题翻译：用于同步数据的方法和系统
公开(公告)号：US06802019B1
公开(公告)日：2004-10-05
申请号：US09596025
申请日：2000-06-15
申请人： Doug Lauder
发明人： Doug Lauder
IPC分类号： H04L700
CPC分类号： H04L65/605 , H04L29/06027 , H04L65/4038 , H04N7/15 , H04N21/23614 , H04N21/242 , H04N21/4305 , H04N21/4348 , H04N21/8547
摘要： A method and system that synchronizes time-related data in a digital processing system. The data to be synchronized includes display data such as audio or video data and command data such as uniform resource locators., The data is encoded with time indicators that allow the media data, through the execution of a set of instructions, to be processed synchronously with the display data.
摘要翻译：一种在数字处理系统中同步时间相关数据的方法和系统。要同步的数据包括诸如音频或视频数据的显示数据以及诸如统一资源定位符的命令数据。该数据用时间指示符进行编码，这些时间指示符通过执行一组指令被同步处理来允许媒体数据与显示数据。

7. 发明授权

US06799280B1 System and method for synchronizing data transfer from one domain to another by selecting output data from either a first or second storage device 有权
标题翻译：通过从第一或第二存储设备选择输出数据来同步从一个域到另一个域的数据传输的系统和方法
公开(公告)号：US06799280B1
公开(公告)日：2004-09-28
申请号：US09477488
申请日：2000-01-04
申请人： Robin W. Edenfield , Christopher D. Bryant
发明人： Robin W. Edenfield , Christopher D. Bryant
IPC分类号： H04L700
CPC分类号： H04L7/02 , H04L7/0045
摘要： An interface circuit is disclosed for synchronizing the transfer of data from a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal, where the phase and frequency relationships of the first and second clock signals are known. The interface circuit comprises: 1) a flip-flop having a data input for receiving a first data signal from the first clock domain, a clock input for receiving the first clock signal, and an output; 2) a latch having a data input coupled to the flip-flop output, a clock input for receiving a gating signal, and an output; and 3) a multiplexer having a first data input coupled to the flip-flop output, a second data input coupled to the latch output, and a selector input for selecting one of the first and second data inputs for the multiplexer output.
摘要翻译：公开了一种接口电路，用于使来自第一时钟信号驱动的第一时钟域的数据的传输与由第二时钟信号驱动的第二时钟域同步，其中第一和第二时钟信号的相位和频率关系是已知的。接口电路包括：1）触发器，具有用于从第一时钟域接收第一数据信号的数据输入端，用于接收第一时钟信号的时钟输入端和输出端; 2）具有耦合到触发器输出的数据输入的锁存器，用于接收门控信号的时钟输入和输出; 以及3）多路复用器，其具有耦合到所述触发器输出的第一数据输入，耦合到所述锁存器输出的第二数据输入，以及用于选择所述多路复用器输出的第一和第二数据输入之一的选择器输入。

8. 发明授权

US06782066B1 Method and system for detecting frame slips in a digital communications channel 有权
标题翻译：用于检测数字通信信道中的帧滑移的方法和系统
公开(公告)号：US06782066B1
公开(公告)日：2004-08-24
申请号：US09231034
申请日：1999-01-14
申请人： Michael G. Nicholas , Vladimir G. Parizhsky
发明人： Michael G. Nicholas , Vladimir G. Parizhsky
IPC分类号： H04L700
CPC分类号： H04J3/0608 , H04J3/125 , H04J3/14
摘要： A method and system for detecting frame slips due to loss of synchronization in a digital communication channel is described. In an illustrative embodiment, a synchronization bit pattern is periodically embedded in the digital data stream. In a described embodiment, the sign bits of the octets of every N frame of data is robbed to form a periodic control channel carrying the synchronization bit pattern. The control channel can be monitored at the appropriate intervals to detect the appropriate synchronization bit pattern. Failure to detect the synchronization bit pattern at the appropriate interval indicates a loss of synchronization such as a frame slip.
摘要翻译：描述了由于数字通信信道中的同步丢失而检测帧滑动的方法和系统。在说明性实施例中，周期性地将数据数据流中嵌入同步位模式。在所描述的实施例中，每N个数据帧的八位字节的符号位被抢占以形成携带同步位模式的周期性控制信道。可以以适当的间隔监视控制信道，以检测适当的同步位模式。未能以适当的间隔检测同步位模式表示失去同步，例如帧滑移。

9. 发明授权

US06775341B2 Time recovery circuit and method for synchronizing timing of a signal in a receiver to timing of the signal in a transmitter 有权
标题翻译：时间恢复电路和方法，用于将接收机中的信号定时与发射机中的信号定时同步
公开(公告)号：US06775341B2
公开(公告)日：2004-08-10
申请号：US10300987
申请日：2002-11-21
申请人： Fan Wang , Jiangnan Jason Chen , Philip Yuanping Zhou
发明人： Fan Wang , Jiangnan Jason Chen , Philip Yuanping Zhou
IPC分类号： H04L700
CPC分类号： H04B1/7085
摘要： The present invention is a time recovery circuit and method for synchronizing timing of a signal in a receiver to timing of the signal in a transmitter. A plurality of samples of the early-late correlation difference are taken around the equilibrium point on the S-curve where the time error is zero. A recursive algorithm is used to compute the time adjustment necessary to time align the transmitter and the receiver by minimizing the squared estimation error.
摘要翻译：本发明是用于将接收机中的信号的定时与发射机中的信号的定时同步的时间恢复电路和方法。在时间误差为零的S曲线上的平衡点周围采取多个早期相关差异的样本。递归算法用于计算通过最小化平方估计误差来对发射机和接收机进行时间校准所需的时间调整。

10. 发明授权

US06769093B1 Synchronization of a communications system 有权
标题翻译：通信系统的同步
公开(公告)号：US06769093B1
公开(公告)日：2004-07-27
申请号：US09788171
申请日：2001-02-14
申请人： Abraham Krieger
发明人： Abraham Krieger
IPC分类号： H04L700
CPC分类号： H04N21/4382 , H04J3/0608 , H04L1/005 , H04L1/0065 , H04L1/0075 , H04N21/2383
摘要： A receiver in which sync data detection logic detects unencoded sync data at block boundaries of blocks encoded symbols received over a communications channel. Based on the detection of the sync data, the sync data detection logic determine synchronization information for one or more components of the receiver. It may also determine one or more system parameters by counting the number of symbols between successive instances of the sync data.
摘要翻译：一种接收机，其中同步数据检测逻辑在通过通信信道接收的块编码符号的块边界处检测未编码的同步数据。基于同步数据的检测，同步数据检测逻辑确定接收机的一个或多个组件的同步信息。它还可以通过对同步数据的连续实例之间的符号数进行计数来确定一个或多个系统参数。

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