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1. 发明申请

WO2022001780A1 绝缘体上半导体结构的制造方法审中-公开
公开(公告)号：WO2022001780A1
公开(公告)日：2022-01-06
申请号：PCT/CN2021/101802
申请日：2021-06-23
申请人：中芯集成电路（宁波）有限公司上海分公司
发明人：黄河 , 丁敬秀 , 向阳辉
IPC分类号： H01L21/762 , H01L21/02 , H01L21/263 , H01L21/306 , H01L21/3065
摘要：一种绝缘体上半导体结构的制造方法，通过在第一离子浓掺杂的第一晶圆（10）上形成第二离子轻掺杂的半导体层（11），并在半导体层（11）的表面上形成第一氧化键合层（12），在第二晶圆（20）的表面上形成第二氧化键合层（21），进一步键合第一氧化键合层（12）和第二氧化键合层（21），以将第一晶圆（10）键合到第二晶圆（20）上，之后通过刻蚀工艺去除第一晶圆（10），以暴露出半导体层（11），进而形成绝缘体上半导体结构，工艺简单，易于执行，且可以精确控制形成的绝缘体上半导体结构的顶层硅的厚度，使得绝缘体上半导体结构中的顶层硅的膜厚较薄，满足高性能的器件的制造需求。

2. 发明申请

WO2021201216A1 半導体装置および半導体装置の製造方法审中-公开
公开(公告)号：WO2021201216A1
公开(公告)日：2021-10-07
申请号：PCT/JP2021/014146
申请日：2021-04-01
申请人：富士電機株式会社
发明人：内田　美佐稀 , 吉村　尚 , 瀧下　博 , 窪内　源宜 , 根本　道生
IPC分类号： H01L21/263 , H01L21/265 , H01L21/322 , H01L21/8234 , H01L27/06 , H01L29/06 , H01L29/78 , H01L29/739 , H01L21/336
摘要：半導体基板の下面側に配置され、２個以上のドーピング濃度ピークを有する、第１導電型のバッファ領域と、バッファ領域と半導体基板の上面との間に配置され、深さ方向において５０μｍ以上の長さを有し、バルク・ドナー濃度よりもドナー濃度が高い第１導電型の高濃度領域と、バッファ領域と半導体基板の下面との間に配置され、高濃度領域よりもドーピング濃度の高い第１導電型または第２導電型の下面領域とを備え、バッファ領域のドーピング濃度ピークのうち、半導体基板の下面に最も近い最浅ドーピング濃度ピークは、他のドーピング濃度ピークよりも高濃度の水素ドナーの濃度ピークであり、最浅ドーピング濃度ピークのピーク濃度Ａと、他のドーピング濃度ピークの平均ピーク濃度Ｂとの比Ａ／Ｂが２００以下である半導体装置を提供する。

3. 发明申请

WO2016066889A1 A METHOD OF FORMING A GRAPHENE OXIDE-REDUCED GRAPHENE OXIDE JUNCTION 审中-公开
标题翻译：形成氧化亚芳基氧化烯键的方法
公开(公告)号：WO2016066889A1
公开(公告)日：2016-05-06
申请号：PCT/FI2015/050714
申请日：2015-10-21
申请人： NOKIA TECHNOLOGIES OY
发明人： WEI, Di , ALLEN, Mark
IPC分类号： H01M4/06 , H01L21/263 , C01B31/04
CPC分类号： H01M6/40 , H01L21/263 , H01M4/0414 , H01M4/583 , H01M6/32
摘要： A method comprising: a deposition step comprising depositing a layer of graphene oxide; a deposition step comprising selectively exposing a region of the deposited graphene oxide layer to electromagnetic radiation to form a region of reduced graphene oxide adjacent to a neighbouring region of unexposed graphene oxide, the graphene oxide and adjacent reduced graphene oxide regions forming a junction therebetween to produce a graphene oxide-reduced graphene oxide junction layer; and repeating the deposition and exposure steps for one or more further respective layers of graphene oxide, over an underlying graphene oxide-reduced graphene oxide junction layer, to produce an apparatus in which the respective junctions of the graphene oxide- reduced graphene oxide layers, when considered together, extend in the third dimension.
摘要翻译：一种方法，包括：沉积步骤，包括沉积氧化石墨烯层; 沉积步骤包括选择性地将沉积的氧化石墨烯层的区域暴露于电磁辐射以形成与未曝光的氧化石墨烯的相邻区域相邻的还原石墨烯氧化物的区域，氧化石墨烯和邻近的还原石墨烯氧化物区域之间形成连接以产生氧化石墨烯氧化物还原石墨烯氧化物结层; 并且在氧化还原氧化石墨烯氧化物接合层上方，在氧化还原氧化石墨烯氧化物接合层之上重复一个或多个其它相应的氧化石墨烯层的沉积和曝光步骤，以产生其中氧化石墨烯氧化物还原的石墨烯氧化物层的各个结点当一起考虑，延伸到第三维度。

4. 发明申请

WO2006015328A3 PULSE THERMAL PROCESSING OF FUNCTIONAL MATERIALS USING DIRECTED PLASMA ARC 审中-公开
标题翻译：使用方向等离子体弧的功能材料的脉冲热处理
公开(公告)号：WO2006015328A3
公开(公告)日：2006-08-03
申请号：PCT/US2005027301
申请日：2005-08-01
申请人： UT BATTELLE LLC , OTT RONALD D , BLUE CRAIG A , DUDNEY NANCY J , HARPER DAVID C
发明人： OTT RONALD D , BLUE CRAIG A , DUDNEY NANCY J , HARPER DAVID C
IPC分类号： C23C4/18 , B05D3/14 , C23C2/26 , G11B5/84 , H01L21/263 , H01L21/268 , H01L31/00
CPC分类号： H01L21/324 , B05D3/148 , B82Y30/00 , C23C2/26 , C23C4/18 , C23C26/00 , G11B5/84 , H01L31/0322 , H01L31/1864 , Y02E10/541 , Y02P70/521
摘要： A method of thermally processing a material includes the steps of providing an article having a surface film disposed on a substrate, and exposing the thin film to at least one incident pulse of infrared comprising radiation at a power density of at least 0.1 kW/cm 2 emitted from a directed plasma arc to thermally process the thin film. The at least one pulse has a duration of no more than 10 s. The method provides a radiation intensity and spectrum of radiation capable of heating the surface film to the desired temperature while allowing the substrate to remain at a lower temperature. This feature permits use of substrates that generally are not high temperature tolerant, such as certain polymer substrates.
摘要翻译：一种热处理材料的方法包括以下步骤：提供具有设置在基底上的表面膜的制品，并将薄膜暴露于至少一个红外线的入射脉冲，其中包括以至少0.1kW / cm 2的功率密度的辐射， SUP> 2 从定向等离子体电弧发射，以热处理薄膜。该至少一个脉冲的持续时间不超过10秒。该方法提供辐射强度和能够将表面膜加热至所需温度的辐射光谱，同时允许基底保持在较低的温度。该特征允许使用通常不耐高温的基底，例如某些聚合物基底。

5. 发明申请

WO01080293A1 METHOD OF CRYSTALLISING A SEMICONDUCTOR FILM 审中-公开
标题翻译：晶体析出薄膜的方法
公开(公告)号：WO01080293A1
公开(公告)日：2001-10-25
申请号：PCT/EP2001/003760
申请日：2001-04-03
IPC分类号： H01L21/336 , H01L29/786 , H01L21/20 , H01L21/263
CPC分类号： H01L29/66757 , H01L29/78675
摘要： A method of crystallising a semiconductor film (3) deposited on a supporting substrate (1,2) is disclosed together with apparatus for the same. The method comprising the steps of (a) with a laser (5), exposing each of a series of discrete regions (a to n) of the semiconductor film to one or more laser beam (4) pulses (an "exposure"); (b) monitoring the energy output of the laser (5); and (c) if the energy output of the laser (5) during an exposure of a discrete region (a to n) exceeds a predetermined threshold, re-exposing that discrete region to one or more laser beam (4) pulses. Also disclosed is a TFT (12) manufactured by said method and active matrix device (20) comprising a row (24) and column (23) array of active elements (22), each having such a switching TFT (12).
摘要翻译：公开了沉积在支撑基板（1,2）上的半导体膜（3）的结晶方法及其装置。该方法包括以下步骤：（a）使用激光（5），将半导体膜的一系列离散区域（a至n）中的每一个暴露于一个或多个激光束（4）脉冲（“曝光”）; （b）监测激光器的能量输出（5）; 和（c）如果在离散区域（a至n）的曝光期间激光器（5）的能量输出超过预定阈值，则将该离散区域再曝光到一个或多个激光束（4）脉冲。还公开了由所述方法制造的TFT（12）和有源矩阵器件（20），其包括有源元件（22）的行（24）和列（23）阵列，每个具有这种开关TFT（12）。

6. 发明申请

WO00017094A1 METHOD FOR PRODUCING NANOMETER STRUCTURES ON SEMICONDUCTOR SURFACES 审中-公开
标题翻译：用于生产纳米结构ON SEMICONDUCTOR曲面
公开(公告)号：WO00017094A1
公开(公告)日：2000-03-30
申请号：PCT/DE1999/002998
申请日：1999-09-18
IPC分类号： B81B1/00 , B81C1/00 , H01L21/20 , H01L21/263 , H01L31/0296
CPC分类号： B82Y30/00 , B82Y10/00
摘要： The invention relates to a method for producing regular nanometer structures on semiconductor surfaces, especially regular pyramid and wave structures, which comprise a narrow size distribution and dimensions ranging from 2 to 100 nm, especially 10-60 nm, particularly in diameter or width and height. The invention is characterized in that a semiconductor material is used which is comprised of at least two and preferably two components thus forming a compound semiconductor. In addition, optionally neutralized noble gas ions from an ion source comprising an energy ranging from 10 to 50000 eV, especially 50-2000 eV, are directed onto said compound semiconductor material, with which, under a vacuum and by means of ion sputtering, the surface of the material is removed until the nanometer structure is produced.
摘要翻译：本发明描述了一种方法用于常规纳米结构的制备中，特别是经常金字塔和波状结构，具有窄粒度分布和2至100纳米的尺寸，特别是10-60纳米，特别是在直径或宽度和高度，在半导体表面上，其特征在于，使用半导体材料，其优选地由两个部件由至少两个，即是化合物半导体和 - 任选地，中和 - 稀有气体离子从离子源与能量10-50000伏特，特别涉及50-2000 EV至该化合物半导体材料与该材料的表面在真空下，通过溅射，该纳米结构的存在是离子的手段尽可能除去。

7. 发明申请

WO2022087524A1 ELECTRICAL DISCHARGE MACHINING OF SEMICONDUCTORS 审中-公开
公开(公告)号：WO2022087524A1
公开(公告)日：2022-04-28
申请号：PCT/US2021/056460
申请日：2021-10-25
申请人： NIELSON SCIENTIFIC, LLC
发明人： NIELSON, Gregory
IPC分类号： H01L21/263 , H01L21/268 , H01L21/423 , H01L21/428
摘要： An electrical discharge machining system includes a semiconductor workpiece, a voltage source, an EDM tool, and an illumination system. The illumination system is configured to illuminate the semiconductor workpiece in order to increase the conductivity of the semiconductor workpiece. The voltage source establishes an electric potential difference between the workpiece and the EDM tool while the illumination system illuminates the semiconductor workpiece. The electric potential difference is such that an electrical discharge occurs between the workpiece and the EDM tool, thereby removing material from the workpiece.

8. 发明申请

WO2022001779A1 绝缘体上半导体结构的制造方法审中-公开
公开(公告)号：WO2022001779A1
公开(公告)日：2022-01-06
申请号：PCT/CN2021/101801
申请日：2021-06-23
申请人：中芯集成电路（宁波）有限公司上海分公司
发明人：黄河 , 丁敬秀 , 向阳辉
IPC分类号： H01L21/762 , H01L21/02 , H01L21/265 , H01L21/263 , H01L21/306 , H01L21/3065 , H01L21/304
摘要：本发明提供了一种绝缘体上半导体结构的制造方法，先通过对第一晶圆进行P型离子注入，形成了第一离子掺杂层，并将所述第一晶圆划分为由基底晶圆层、第一离子掺杂层和表面晶圆层组成的三明治结构，后通过表面晶圆层表面上形成的第一氧化键合层以及第二晶圆表面上形成的第二氧化键合层，将第一晶圆键合到第二晶圆上，之后先去除基底晶圆层，再通过刻蚀工艺去除第一离子掺杂层，从而形成绝缘体上半导体结构。其中第一离子掺杂层的深度和厚度限定了绝缘体上半导体结构的顶层半导体层厚度，且该第一离子掺杂层为腐蚀增强层，能通过刻蚀工艺快速去除且不会对顶层半导体层造成不必要的损伤，以使得顶层半导体层更薄、膜厚更均匀。

9. 发明申请

WO2019160674A1 PVD TITANIUM DIOXIDE FORMATION USING SPUTTER ETCH TO HALT ONSET OF CRYSTALINITY IN THICK FILMS 审中-公开
公开(公告)号：WO2019160674A1
公开(公告)日：2019-08-22
申请号：PCT/US2019/015416
申请日：2019-01-28
申请人： APPLIED MATERIALS, INC.
发明人： ARMSTRONG, Karl , FU, Jinxin
IPC分类号： C23C14/58 , C23C14/08 , C23C14/34 , C23C14/50 , H01L21/263 , H01J37/32
摘要： Embodiments described herein provide methods of forming amorphous or nano-crystalline ceramic films. The methods include depositing a ceramic layer on a substrate using a physical vapor deposition (PVD) process, discontinuing the PVD process when the ceramic layer has a predetermined layer thickness, sputter etching the ceramic layer for a predetermined period of time, and repeating the depositing the ceramic layer using the PVD process, the discontinuing the PVD process, and the sputter etching the ceramic layer until a ceramic film with a predetermined film thickness is formed.

10. 发明申请

WO2019125934A1 METHOD FOR CONTROLLING THE AMOUNT OF RADIATION HAVING A PREDETERMINED WAVELENGTH TO BE ABSORBED BY A STRUCTURE DISPOSED ON A SEMICONDUCTOR 审中-公开
公开(公告)号：WO2019125934A1
公开(公告)日：2019-06-27
申请号：PCT/US2018/065634
申请日：2018-12-14
申请人： RAYTHEON COMPANY
发明人： CHENG, Kezia , ALAVI, Kamal, Tabatabaie , WILLIAMS, Adrian, D. , MACDONALD, Christopher, J. , HWANG, Kiuchul
IPC分类号： H01L21/04 , H01L29/45 , H01L21/263 , H01L21/285
摘要： A stack of layers providing an ohmic contact with the semiconductor, a lower metal layer of the stack is disposed in direct contact with the semiconductor; and a radiation absorption control layer disposed over the lower layer for controlling an amount of the radiant energy to be absorbed in the radiation absorption control layer during exposure of the stack to the radiation during a process used to alloy the stack with the semiconductor to form the ohmic contact.

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