会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 21. 发明授权
    • Method for measuring phase locked loop bandwidth parameters for high-speed serial links
    • 用于测量高速串行链路的锁相环带宽参数的方法
    • US08254515B2
    • 2012-08-28
    • US12410413
    • 2009-03-24
    • Dongming LouPengfei HuJunqiang ShangXin Liu
    • Dongming LouPengfei HuJunqiang ShangXin Liu
    • H03D3/24H04Q1/20H04L23/00
    • H03L7/08H04L7/033
    • A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator; determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.
    • 用于测量高速串行链路的锁相环带宽参数的方法包括以下步骤:利用频率发生器启动等于参考频率的锁相环的时钟输入的抖动频率; 使用参考频率的波形分析器确定锁相环的时钟输出的参考抖动幅度值,参考抖动幅度值是参考频率时钟输出的时间间隔误差抖动趋势的函数; 并且通过频率发生器调整时钟输入的抖动频率,直到时钟输出的经调整的抖动幅度值达到由波形分析器确定的目标值,调整后的抖动幅度是时钟的时间间隔误差趋势的函数 以调整频率输出。
    • 25. 发明授权
    • Method for reliable injection of deterministic jitter for high speed transceiver simulation
    • 可靠地注入高速收发器仿真确定性抖动的方法
    • US08073043B2
    • 2011-12-06
    • US11904687
    • 2007-09-27
    • Xin LiuLiang ZhangJiang Li Xin
    • Xin LiuLiang ZhangJiang Li Xin
    • H04B3/46H04L7/00G06F1/04
    • H04B3/462
    • A method and a corresponding system for characterizing the performance of a clock and data recovery circuit in a digital transceiver is presented. The method comprises phase modulating a jitter-free data signal by a testing signal having added data jitter and measuring the time the clock and data recovery system takes to achieve bit lock of a phase modulated signal. Data uncorrelated timing jitter corresponding to a user defined probability distribution is included in the jitter testing signal. Utilization of a variable probability distribution in generating data uncorrelated timing jitter, as provided by the present invention, allows for greater flexibility and accuracy in clock and data recovery circuit testing and characterization.
    • 提出了一种用于表征数字收发器中的时钟和数据恢复电路的性能的方法和相应的系统。 该方法包括通过具有附加的数据抖动的测试信号对无抖动数据信号进行相位调制,并测量时钟和数据恢复系统为实现相位调制信号的位锁定所需的时间。 与用户定义的概率分布相对应的数据不相关的定时抖动被包括在抖动测试信号中。 利用可变概率分布来产生数据不相关的定时抖动,如本发明所提供的,允许在时钟和数据恢复电路测试和表征中具有更大的灵活性和准确性。