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序号	专利名	申请号	申请日	公开（公告）号	公开（公告）日	发明人
41	Device and method for generating an oscilloscope trigger signal from a video signal	EP92202368.4	1992-07-30	EP0527526A1	1993-02-17	Boelart, Eduardo
A sync separator separates vertical, field and horizontal synchronization signals from a video signal processed by a circuit under test which exhibits an artifact in the video. The cause of the artifact in the circuit under test is to be located using an oscilloscope. A line select circuit includes a delay responsive to the separated vertical and field signals for generating a marker signal and for positioning the marker signal via observation of the display produced by video signal under test. A trigger signal and marker generator refines the marker signal by causing the boundaries of the marker signal to coincide with corresponding horizontal sync pulses and produces an oscilloscope trigger signal having a transition which is formed by one of those boundaries. A combiner circuit combines the refined marker signal with the video signal under test for display so that the marker signal via the delay can be positioned on a region of interest in the video display. The trigger signal triggers the oscilloscope so that the oscilloscope displays that portion of the video defined by the so positioned marker signal.
42	Probability density histogram display	EP87309684.6	1987-11-02	EP0267722A3	1989-10-11	Johnson, Dana L..
Disclosed is a probability density histogram display (200A,210A,220A,230A,310) for a digital oscilloscope (5) which shows a probability density histogram display of an input signal waveform alongside the conventional voltage-versus-time time-domain display (200,210,220,230,305) of the waveform. The histogram (315) shows the relative frequency of occurrence of voltage amplitude levels of the waveform (300). The histogram is optional and shown simultaneously with the time-domain display of the waveform.
43	HARMONIC SAMPLING LOGIC ANALYZER.	EP86905511	1986-08-18	EP0235250A4	1989-03-16	BLANDING CURTIS J
A logic analyzer employs a phase locked loop (47, 49, 51, 53, etc.) adapted to be driven by a clock signal from a system under test in order to generate a sampling clock (45) that is synchronized in time relationship therewith and a selectable integer multiple in frequency thereof. The time relationship of the system and sampling clocks is controllable.
44	2현상 오실로스코프의 화면분할 표시회로	KR1019880006002	1988-05-21	KR100041896B1	1991-05-20	박상신

45	오실로스코프의 입력 파형과 그라운드 라인 동시 표시 회로	KR1019880006914	1988-06-09	KR1019900000705A	1990-01-31	박상신
내용 없음
46	회로해석장치	KR2020010002797	2001-02-06	KR200228964Y1	2001-07-19	김순일
본 고안은 회로해석장치에 관한 것으로써, 더욱 상세하게는 측정목적물의 전류, 전압 특성곡선이 시각화되어 나타나는 회로해석장치로서, 2개의 출력단이 구비된 교류발생기와, 외부부품에 접촉연결되어 전압및 전류가 검출되는 검출부와, 상기 검출기의 전압신호및 전류신호가 표시되는 표시부와, 외부능동소자의 구동입력으로 제공되는 출력을 발생시키는 펄스발생기와, 외부집적회로의 클락입력을 출력으로 발생시키는 클락발생기를 포함하여 구성된 회로해석장치에 관한 것이다. 이에 따라 전압과 전류가 수직축과 수평축상에 표현되어 측정목적물의 전압, 전류특성곡선이 상기 표시부에 시각화되어 나타나는 이점이 있다. 또한 콘덴서나 코일이 측정되면 리사쥬도형으로 나타나며, 리사쥬도형의 모양을 보고 콘데서나 코일의 임피던스가 측정되는 이점이 있다.
47	신호파형표시장치및표시방법	KR1019940023126	1994-09-14	KR1019950009265A	1995-04-21	오자와겐따로
입력신호의 파형을 디스플레이(1)상에 표시하는 장치에 있어서, 동기검출회로(10)와, 스위프발생회로(11)와, 수평축 구동회로(12)와, 절환회로(7)와, 가변게인증폭기(8)와, 수직축 구동회로(9), 및 수평위치 조정회로(13)를 구비하는 신호파형의 표시장치가 개시되어 있다. 상기 수평축 구동회로(12)는 동기검출회로(10)로부터의 동기검출펄스를 N(N=1,2,...)으로 나눔으로써 얻어진 스위프트리거신호와 동기하여 스위프발생회로(11)에서 발생된 스위프신호에 근거하여 디스플레이(1)의 수평축을 구동시킨다. 상기 절환회로(7)는 입력신호 및 커서신호를 고속으로 번갈아 전달하여 복합된 입력/커서신호를 가변게인증폭기를 통해 수직축 구동회로(9)로 제공하도록한다. 상기 수직위치 조정회로(13)는 수직축 구동회로(9)로 스위프트리거신호와 단계적으로 가변동기하여 수직위치 조정신호를 발생시키고, 복합된 입력/커서 및 수직위치 조정신호가 조합되어 수직축 구동신호를 제공한다. 따라서, 커서를 갖는 파형중 적어도 두 개의 분리된 부분들은 디스플레이의 좌측 및 우측부상에 확대/분할표시모드(N≥2)로 표시되고, 커서를 갖는 전체파형은 디스플레이상에서 정상표시코드(N=1)로 표시된다.
48	Measuring system and method	US15871801	2018-01-15	US11061053B2	2021-07-13	Gerd Bresser; Friedrich Reich
A measuring system for measuring signals with multiple measurement probes comprises a multi probe measurement device comprising at least two probe interfaces that each couple the multi probe measurement device with at least one of the measurement probes, a data interface that couples the multi probe measurement device to a measurement data receiver, and a processing unit coupled to the at least two probe interfaces that records measurement values via the at least two probe interfaces from the measurement probes, wherein the processing unit is further coupled to the data interface and provides the recorded measurement values to the measurement data receiver, and a measurement data receiver comprising a data interface, wherein the data interface of the measurement data receiver is coupled to the data interface of the multi probe measurement device.
49	Programmable interface-based validation and debug	US14038743	2013-09-26	US09152520B2	2015-10-06	Anshul Gahoi; Raghavendra Santhanagopal; Pradeep Kumar Babu
A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under test to the test fixture. A programmable logic interface is communicatively coupled to the test connector and is arranged to receive a downloadable test bench, where the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first test control bus. A multiplexer is arranged to selectively couple one of the first test control bus and a second test control bus to a shared test bus that is coupled to the test connector, where the second test control bus is arranged to apply test vectors from a second set of test vectors provided by, for example, a debugger that is operated by a human.
50	Context sensitive toolbar	US10015125	2001-12-11	US06907365B2	2005-06-14	Lawrence Steven Salant; Anthony Cake; John Gregory Hannes
An oscilloscope apparatus, comprising a display for displaying a plurality of objects, a toolbar displayed on the display, and a user interface for selecting an object. The display displays one or more functions on the toolbar corresponding to the selected object.
51	Modular re-useable bus architecture	US82457	1998-05-20	US06128758A	2000-10-03	Christopher Hall; Rajat Sewal; Jumana Muwafi
A modular reusable bus architecture enhances testability of an integrated computer system in which multiple modules communicate over a system bus. Under the modular reusable bus architecture, the system bus can be configured to operate in different operation modes. In one embodiment, the bus architecture provides a test mode for testing an individual module within the integrated computer system, separate from the other modules. In another embodiment, the bus architecture configures the system bus to provide access to configuration registers and memory units disposed within each module, otherwise inaccessible in normal system operation. The modular reusable architecture can support any types and any number of modules, including modules incorporating analog and digital circuitry, and modules operating under different clock domains.
52	Error recovery in a network having cascaded hubs	US858995	1997-05-20	US5768250A	1998-06-16	Alan R. Albrecht
A network system includes end nodes which are connected to a plurality of cascaded hubs. Each hub is able to generate a network error packet when a timeout is detected. More specifically, a first hub starts a first timer upon the first hub acknowledging a grant to a first device connected to a first port of the first hub. Upon expiration of the first timer without the first hub beginning to receive a first network packet over the first port, the first hub begins to send a first error packet to a second device connected to the first hub. If the first hub begins to receive a second error packet over the first port after expiration of the first timer and before the first hub has completed sending the first error packet, the first hub appends the second error packet to the first error packet. If the first hub does not begin to receive any error packet over the first port before completely sending the first error packet, the first hub marks the first port as failed.
53	Method and apparatus for obtaining voltage-isolated measurement channels with an isolation transformer and multiplier	US526650	1995-09-11	US5594329A	1997-01-14	Rudolf G. van Ettinger; Martinus P. Eikendal
A method and apparatus for obtaining a voltage-isolated measurement channel in a measurement instrument is provided. An input signal is multiplied with a clock signal to obtain a modulated input signal that is coupled to an input winding of a balanced transformer. The modulated input signal is electromagnetically coupled from the input winding to an output winding. At the same time, the input winding and the output winding are voltage-isolated, meaning that the portion of the measurement channel coupled to the input winding is "floated" with the input signal whereas the remaining portion of the measurement channel is referenced to instrument ground. A sampling circuit coupled to the output winding samples the modulated input signal in the manner of a synchronous detector to extract the original input signal voltage which is provided to an analog to digital converter which generates the digital measurement values. Each measurement channel is voltage-isolated from the instrument and from all other measurement channels in the instrument.
54	Multiplexing instrumentation preamplifier	US379416	1995-01-27	US5586114A	1996-12-17	Thomas F. Uhling; Eddie A. Evel
An oscilloscope preamplifier includes N inputs and Z outputs. A programmable cross-point multiplexer provides a first operating mode in which each of N inputs is connected to a different output thereby providing a preamplifier with Z channels, a second operating mode in which one input is multiplexed to all the outputs which are interleaved to maximize the sampling rate, and a range of operating modes in between. The programmable multiplexer includes a switching amplifier connected between each input and each output. Dials on the preamp select the mode by causing a microprocessor to program latches which activate or deactivate the switching amplifiers. A voltage divider is connected across inputs of the multiplexer to provide a programmable attenuator with selectable attenuation levels.
55	Oversampled logic analyzer	US197421	1994-02-16	US5526286A	1996-06-11	Tim E. Sauerwein; Craig L. Overhage; Donald C. Kirkpatrick
A logic analyzer acquires all data and clock signal inputs asynchronously at high speed using a digital FISO (10) to produce a plurality of parallel high-speed data samples within each cycle of an internal system clock (95). The plurality of parallel high-speed data samples describe the sequential behavior of one of the input signals during one period of the internal system clock. One of the plurality of parallel high-speed data samples is then selected to be the single data sample that is stored in the acquisition memory (80) for that clock cycle. The selection process includes a skew adjustment (20), clock edge detection and selection (50), aligning the sample associated with the detected and selected clock edge to a reference location (60), and selecting (70) as the single sample to be stored a sample having a relationship to the reference location that is determined by setup and hold adjustment data. The transitions detected are enabled (102) and ORed (108) to produce a setup and hold violation signal only if they are within the interval established by a set of setup and hold window mask signals.
56	Self-aligning sampling system and logic analyzer comprising a number of such sampling systems	US619848	1990-11-29	US5159337A	1992-10-27	Willem Lankreijer
A self-aligning sampling system for sampling digital signals, for example in a logic analyzer includes an adjustable delay line fed by a system clock signal which delay line has tapping points for further clock signals. In conjunction with the system clock, the further clock signals are used to take several samples of the digital signal in a time slot of the system clock. In order to achieve equidistant sampling even in the case of a large process spread in elementary delay units of the delay line, the delay line is calibrated. The system clock is then connected to the data input and expressed in elementary delay units on the basis of measurement. Subsequently, the delay line between clock signal tapping points is adjusted on the basis thereof.
57	Method for acquiring data in a logic analyzer	US414337	1989-09-29	US5067130A	1991-11-19	Ronald M. Jackson
A logic analyzer stores the activity around the last in a series of triggering events while also storing the activity around several other triggering events immediately preceding the last trigger. The acquisition memory is first positioned into a number, N, of memory sections and the trigger condition of interest is defined. Then repeated acquistions are performed using this same trigger condition. At first, data from each of these acquisitions is stored in each one of the number of memory sections. When all of the memory sections have been filled once, if the trigger condition is still occurring, the acquisition memories are reused in the same order in which they were originally used as many times as necessary until it is ascertained that the trigger condition is no longer occurring or some external conditon has changed, at which time the logic analyzer is stopped. One of the memory sections then contains the data that occurred in the vicinity of the last trigger. Another of the memory sections contains data reflecting the activity that immediately preceded the stopping of the logic analyzer. The remaining N-2 memory sections contain data that occurred in the vicinity of the triggers that immediately preceded the last trigger. Timestamping the acquired data allows the timing relationships involved to be reconstructed.
58	Logic analyzer	US272158	1988-11-16	US4924468A	1990-05-08	Dieter K. Horak; Rudolf Wieczorek
A logic analyzer for measuring logic signals which are delivered by a number of targets and which are not correlated in time. To incorporate the actual time features and relationships between the data signals of various targets the logic analyzer has at least one acquisition module which can be connected to an associated target or data source. The acquisition modules have various circuit arrangements which choose between the system's internal constant-frequency, or the external target generated, clock signal for a sampling signal, and then samples and synchronizes the time uncorrelated data signals. The data signals are then compared with predetermined patterns and coincidence is indicated.
59	Logic analyzer	US797205	1985-11-12	US4730314A	1988-03-08	Kazuo Noguchi
A state analysis section which loads first input data into a first data memory for each change in state of the data and a timing analysis section which loads second input data into a second data memory with a fixed period are provided. The loading intervals of the first input data are measured by a data interval measuring circuit and each measured data loading interval is stored in a data loading interval memory. When the first and second input data are detected to match preset data in first and second trigger detectors, respectively, the detected outputs are delayed by first and second delay means, and by the outputs of the first and second delay means, the first and second data memories are stopped from the data loading thereinto. The time difference between the stopping of the data loading into both the data memories is measured by a time difference measuring circuit and the measured time difference is stored in a time difference memory. When one of the data stored in one of the first and second data memories is specified by specifying means, data in the other data memory corresponding to the point of time at which the specified data was loaded is detected using the data loading intervals stored in the data loading interval memory and the time difference stored in the time difference memory.
60	Method and apparatus for time-aligning data	US442948	1982-11-19	US4574354A	1986-03-04	Michael A. Mihalik; Gerd H. Hoeren; Michael G. Reiney; James J. Besemer; Steven R. Palmquist
An apparatus for time aligning data acquired by one test instrument with corresponding data acquired by another test instrument is disclosed. A set of binary codes, representative of a set of instructions executed by a microprocessor disposed within a user's prototype circuit, are acquired by said one test instrument. With the acquisition of each of said binary codes, a count is developed in a counter indicative of each said acquisition. A multitude of binary data is acquired, independently of the acquisition of the set of binary codes, by said another test instrument, the multitude of binary data being representative of the functions performed by a set of components present within said user's prototype circuit. The binary codes acquired by said one test instrument and the binary data acquired by said another test instrument each have associated therewith a count developed from said counter. A mini-computer receives the binary codes acquired by said one test instrument, the binary data acquired by said another test instrument, and the counts corresponding thereto. The mini-computer time-aligns the binary data acquired by said another test instrument with the binary codes acquired by said one test instrument, using the counts associated therewith. A display of the time-aligned data is developed on a display device. As a result, when an instruction is executed by the microprocessor of the user's prototype circuit, using said display, it is possible to easily analyze the activity which took place among the components present within the user's prototype circuit as a result of the execution of said instruction by said microprocessor.

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