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41. 发明申请

US20130326101A1 INTERRUPT RETURN INSTRUCTION WITH EMBEDDED INTERRUPT SERVICE FUNCTIONALITY 有权
标题翻译：具有嵌入式中断服务功能的中断返回指令
公开(公告)号：US20130326101A1
公开(公告)日：2013-12-05
申请号：US13997651
申请日：2011-12-22
申请人： Zhen Fang , Xiaowei Jiang , Shihari Makineni , Ramesh G. Illikkal , Ravishankar Iyer
发明人： Zhen Fang , Xiaowei Jiang , Shihari Makineni , Ramesh G. Illikkal , Ravishankar Iyer
IPC分类号： G06F13/24
CPC分类号： G06F9/3016 , G06F9/327 , G06F9/3861 , G06F9/4806 , G06F9/4812 , G06F13/24
摘要： An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.
摘要翻译：描述了在半导体芯片上实现的指令流水线。半导体芯片包括执行单元，以执行中断处理指令。存储电路用于保存不同组的微操作，其中每组微操作都要处理不同的中断。第一逻辑电路，用于执行一组所述微操作组，以处理所述集合设计的中断。第二逻辑电路，用于在所述第一逻辑电路处理所述中断时将程序流返回到调用程序。

42. 发明申请

US20120304087A1 Graphical User Interface for Map Search 有权
标题翻译：地图搜索的图形用户界面
公开(公告)号：US20120304087A1
公开(公告)日：2012-11-29
申请号：US13113889
申请日：2011-05-23
申请人： Brandon Marshall Walkin , Zhen Fang
发明人： Brandon Marshall Walkin , Zhen Fang
IPC分类号： G06F3/048
CPC分类号： G06F3/14 , G06F3/0482 , G06F17/30 , G06F17/30241 , G06F17/30398 , G06F17/3053 , G06F17/3087 , G06Q50/01 , G06T11/00 , G06T11/206 , H04L12/1813 , H04W4/02
摘要： Particular embodiments include a method comprising accessing location data representing a first location of a first user wherein the first location corresponds to geographic coordinates, retrieving image data defining a graphical map from a remote server based on the first location accessing a search query inputted by the first user, retrieving one or more second locations in response to the search query, where the one or more second locations correspond to geographic coordinates, and displaying a first view comprising a list of the one or more second locations overlaying at least a portion of the graphical map, wherein the graphical map includes indicators for the first location and at least one of the one or more second locations in accordance with their respective geographic coordinates.
摘要翻译：具体实施例包括访问表示第一用户的第一位置的位置数据的方法，其中第一位置对应于地理坐标，基于访问由第一位置输入的搜索查询的第一位置检索从远程服务器定义图形映射的图像数据用户，响应于所述搜索查询检索一个或多个第二位置，其中所述一个或多个第二位置对应于地理坐标，以及显示包括覆盖所述图形的至少一部分的所述一个或多个第二位置的列表的第一视图地图，其中所述图形地图包括根据它们各自的地理坐标的所述第一位置和所述一个或多个第二位置中的至少一个的指示符。

43. 发明授权

US08268126B2 Method, equipment and applications for fast complete dissolution and hydrolysis of lignocellulosic biomass 有权
标题翻译：快速完全溶解和水解木质纤维素生物质的方法，设备和应用
公开(公告)号：US08268126B2
公开(公告)日：2012-09-18
申请号：US12671510
申请日：2008-03-28
申请人： Zhen Fang , Chun Fang
发明人： Zhen Fang , Chun Fang
IPC分类号： D21C3/02 , C10G1/00
CPC分类号： C08H8/00
摘要： The invention herein discloses a method and its equipment for fast and complete dissolution and hydrolysis of lignocellulosic biomass. Lignocellulosic biomass is placed in a dilute alkaline solution and then rapidly heated to a temperature between 329˜367° C. to achieve complete dissolution of the lignocellulosic biomass as biomass solution in 0.7˜2 s. The biomass solution is further hydrolyzed rapidly to hydrolysates at homogeneous conditions. The solubilized biomass solution is easy to rapidly hydrolyze into sugars to produce bio-fuels and other value-added products, and to rapidly quench to produce micron particles in the continuous flow equipment at high pressures and high temperatures. The invention herein provides a simple and low-cost method to quickly dissolve and hydrolyze biomass with great potential for a novel biorefinery.
摘要翻译：本发明公开了一种用于木质纤维素生物质的快速和完全溶解和水解的方法及其设备。将木质纤维素生物质置于稀碱溶液中，然后迅速加热至329〜367℃之间，以达到0.7〜2s的生物量溶液完全溶解木质纤维素生物质。生物质溶液在均匀的条件下进一步水解成水解物。溶解的生物质溶液易于快速水解成糖，以生产生物燃料和其他增值产品，并在连续流动设备中在高压和高温下快速淬火以产生微米颗粒。本发明提供了一种简单且低成本的方法，用于快速溶解和水解具有巨大潜力的新生物精炼生物质的生物质。

44. 发明申请

US20060242308A1 Node synchronization for multi-processor computer systems 有权
标题翻译：多处理器计算机系统的节点同步
公开(公告)号：US20060242308A1
公开(公告)日：2006-10-26
申请号：US11113805
申请日：2005-04-25
申请人： John Carter , Randal Passint , Donglai Dai , Zhen Fang , Lixin Zhang , Gregory Thorson
发明人： John Carter , Randal Passint , Donglai Dai , Zhen Fang , Lixin Zhang , Gregory Thorson
IPC分类号： G06F15/16
CPC分类号： G06F15/16 , Y10S707/99952
摘要： A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.
摘要翻译：用于控制一组访问节点对家庭节点（在多模式计算机系统中）的存储器的访问的方法和装置确定该组节点中的每个节点已经访问了存储器，并将完成消息转发到在确定每个节点已访问存储器之后，节点集合。完成消息具有指示节点集合中的每个节点已经访问了家庭节点的存储器的数据。

45. 发明授权

US09395994B2 Embedded branch prediction unit 有权
标题翻译：嵌入式分支预测单元
公开(公告)号：US09395994B2
公开(公告)日：2016-07-19
申请号：US13992723
申请日：2011-12-30
申请人： Xiaowei Jiang , Srihari Makineni , Zhen Fang , Dmitri Pavlov , Ravi Iyer
发明人： Xiaowei Jiang , Srihari Makineni , Zhen Fang , Dmitri Pavlov , Ravi Iyer
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058
摘要： In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
摘要翻译：根据本发明的一些实施例，用于嵌入式控制器的分支预测单元可以与指令提取单元相关联而不是解码级放置。另外，分支预测单元也可以不包括分支预测器。此外，返回地址堆栈可以与指令解码级相关联，并且在结构上与分支预测单元分离。在某些情况下，这种布置减少了分支预测单元的面积以及功耗。

46. 发明授权

US09378164B2 Interrupt return instruction with embedded interrupt service functionality 有权
标题翻译：具有嵌入式中断服务功能的中断返回指令
公开(公告)号：US09378164B2
公开(公告)日：2016-06-28
申请号：US13997651
申请日：2011-12-22
申请人： Zhen Fang , Xiaowei Jiang , Srihari Makineni , Ramesh G. Illikkal , Ravishankar Iyer
发明人： Zhen Fang , Xiaowei Jiang , Srihari Makineni , Ramesh G. Illikkal , Ravishankar Iyer
IPC分类号： G06F13/24 , G06F9/32 , G06F9/38 , G06F9/48
CPC分类号： G06F9/3016 , G06F9/327 , G06F9/3861 , G06F9/4806 , G06F9/4812 , G06F13/24
摘要： An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.
摘要翻译：描述了在半导体芯片上实现的指令流水线。半导体芯片包括执行单元，以执行中断处理指令。存储电路用于保存不同组的微操作，其中每组微操作都要处理不同的中断。第一逻辑电路，用于执行一组所述微操作组，以处理所述集合设计的中断。第二逻辑电路，用于在所述第一逻辑电路处理所述中断时将程序流返回到调用程序。

47. 发明授权

US08631207B2 Cache memory power reduction techniques 有权
标题翻译：高速缓存存储器功耗缩减技术
公开(公告)号：US08631207B2
公开(公告)日：2014-01-14
申请号：US12647461
申请日：2009-12-26
申请人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
发明人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
摘要翻译：描述了提供存储器（诸如高速缓存存储器）中的功耗降低的方法和装置。在一个实施例中，使用虚拟标签来确定是否访问缓存方式。虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。在另一个实施例中，可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。还描述了其它实施例。

48. 发明授权

US08621149B2 Controlling access to a cache memory using privilege level information 有权
标题翻译：使用特权级别信息控制对高速缓存的访问
公开(公告)号：US08621149B2
公开(公告)日：2013-12-31
申请号：US12645788
申请日：2009-12-23
申请人： Zhen Fang , Li Zhao , Ravishankar Iyer , Tong Li , Donald K. Newell
发明人： Zhen Fang , Li Zhao , Ravishankar Iyer , Tong Li , Donald K. Newell
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0895 , G06F12/1491 , Y02D10/13
摘要： In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，高速缓冲存储器包括各自存储环电平标识符的条目，其可以指示存储在条目中的信息的权限级别。该标识符可用于执行对高速缓冲存储器的读取访问。作为示例，耦合到高速缓存存储器的逻辑可以至少部分地基于处理器的当前特权级别和一个或多个高速缓冲存储器的环电平标识符来过滤对所选择的高速缓冲存储器组的一种或多种方式的访问，更多的方式描述和要求保护其他实施例。

49. 发明申请

US20130138843A1 DELEGATING A POLL OPERATION TO ANOTHER DEVICE 有权
标题翻译：将另一个设备的操作删除
公开(公告)号：US20130138843A1
公开(公告)日：2013-05-30
申请号：US13729172
申请日：2012-12-28
申请人： Michael J. Espig , Zhen Fang , Ravishankar Iyer , David J. Harriman
发明人： Michael J. Espig , Zhen Fang , Ravishankar Iyer , David J. Harriman
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/542
摘要： In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于处理从主机处理器接收的注册消息的方法，其中所述注册消息将关于设备的轮询操作从主机处理器委托给另一个组件。来自消息的信息可以存储在轮询表中，并且组件可以发送读请求以轮询该设备并且基于该设备的状态向轮询处理器报告轮询的结果。描述和要求保护其他实施例。

50. 发明授权

US08131944B2 Using criticality information to route cache coherency communications 有权
标题翻译：使用关键性信息来路由缓存一致性通信
公开(公告)号：US08131944B2
公开(公告)日：2012-03-06
申请号：US12156343
申请日：2008-05-30
申请人： Zhen Fang , Liqun Cheng , Sriram R. Vangal
发明人： Zhen Fang , Liqun Cheng , Sriram R. Vangal
IPC分类号： G06F12/00
CPC分类号： G06F12/0822
摘要： In one embodiment, the present invention includes a method for receiving a cache coherency message in an interconnect router from a caching agent, mapping the message to a criticality level according to a predetermined mapping, and appending the criticality level to each flow control unit of the message, which can be transmitted from the interconnect router based at least in part on the criticality level. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从高速缓存代理器接收互连路由器中的高速缓存一致性消息的方法，用于根据预定映射将消息映射到临界级，并将关键性级别附加到每个流控制单元消息，其可以至少部分地基于关键性级别从互连路由器发送。描述和要求保护其他实施例。

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