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1. 发明授权

US08631207B2 Cache memory power reduction techniques 有权
标题翻译：高速缓存存储器功耗缩减技术
公开(公告)号：US08631207B2
公开(公告)日：2014-01-14
申请号：US12647461
申请日：2009-12-26
申请人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
发明人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
摘要翻译：描述了提供存储器（诸如高速缓存存储器）中的功耗降低的方法和装置。在一个实施例中，使用虚拟标签来确定是否访问缓存方式。虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。在另一个实施例中，可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。还描述了其它实施例。

2. 发明申请

US20110161595A1 CACHE MEMORY POWER REDUCTION TECHNIQUES 有权
标题翻译：缓存记忆功率降低技术
公开(公告)号：US20110161595A1
公开(公告)日：2011-06-30
申请号：US12647461
申请日：2009-12-26
申请人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
发明人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
IPC分类号： G06F12/08 , G06F12/00 , G06F1/32
CPC分类号： G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
摘要翻译：描述了提供存储器（诸如高速缓存存储器）中的功耗降低的方法和装置。在一个实施例中，使用虚拟标签来确定是否访问缓存方式。虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。在另一个实施例中，可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。还描述了其它实施例。

3. 发明申请

US20080158770A1 Method of manufacturing circuit board embedding thin film capacitor 有权
标题翻译：制造电路板埋入薄膜电容器的方法
公开(公告)号：US20080158770A1
公开(公告)日：2008-07-03
申请号：US12000125
申请日：2007-12-10
申请人： In Hyung Lee , Yul Kyo Chung , Bae Kyun Kim , Seung Eun Lee , Jung Won Lee
发明人： In Hyung Lee , Yul Kyo Chung , Bae Kyun Kim , Seung Eun Lee , Jung Won Lee
IPC分类号： H01G4/00 , H05K3/30
CPC分类号： H05K1/162 , H01G4/005 , H01G4/33 , H05K3/046 , H05K2201/0108 , H05K2201/0175 , H05K2203/016 , H05K2203/0528 , H05K2203/0537 , H05K2203/107 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155
摘要： A method of manufacturing a circuit board embedding a thin film capacitor, the method including: forming a sacrificial layer on a first substrate; forming a dielectric layer on the sacrificial layer; forming a first electrode layer on the dielectric layer; disposing the first substrate on the second substrate in such a way that the first electrode layer is bonded to a top of a second substrate; decomposing the sacrificial layer by irradiating a laser beam onto the sacrificial layer through the first substrate; separating the first substrate from the second substrate; and forming a second electrode layer on the dielectric layer.
摘要翻译：一种制造嵌入薄膜电容器的电路板的方法，所述方法包括：在第一基板上形成牺牲层; 在所述牺牲层上形成介电层; 在所述电介质层上形成第一电极层; 将第一基板设置在第二基板上，使得第一电极层接合到第二基板的顶部; 通过经由所述第一基板将激光束照射到所述牺牲层上来分解所述牺牲层; 将第一基板与第二基板分离; 以及在所述电介质层上形成第二电极层。

4. 发明授权

US08692391B2 Embedded ball grid array substrate and manufacturing method thereof 有权
标题翻译：嵌入式球栅阵列基板及其制造方法
公开(公告)号：US08692391B2
公开(公告)日：2014-04-08
申请号：US12972310
申请日：2010-12-17
申请人： Tae Sung Jeong , Doo Hwan Lee , Seung Eun Lee
发明人： Tae Sung Jeong , Doo Hwan Lee , Seung Eun Lee
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H05K1/18
CPC分类号： H01L24/11 , H01L23/49827 , H01L23/5389 , H01L24/32 , H01L24/48 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2224/2919 , H01L2224/32155 , H01L2224/48091 , H01L2224/48227 , H01L2224/83001 , H01L2224/838 , H01L2224/85 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad.
摘要翻译：本文公开了嵌入式球栅阵列基板及其制造方法。嵌入式球栅阵列包括：其中具有空腔的芯层; 嵌入在芯层的空腔中的半导体器件; 第一电路层，具有包括在其上形成的引线接合焊盘的电路图案; 第二电路层，其具有包括形成在其上的焊球图案的电路图案; 以及将半导体器件电连接到引线接合焊盘的线。

5. 发明授权

US07943858B2 Thin film capacitor, thin film capacitor-embedded printed circuit board and manufacturing method of thin film capacitor 有权
标题翻译：薄膜电容器，薄膜电容器嵌入式印刷电路板以及薄膜电容器的制造方法
公开(公告)号：US07943858B2
公开(公告)日：2011-05-17
申请号：US12076989
申请日：2008-03-26
申请人： Seung Eun Lee , Yul Kyo Chung , Jung Won Lee , In Hyung Lee , Byung Ik Song
发明人： Seung Eun Lee , Yul Kyo Chung , Jung Won Lee , In Hyung Lee , Byung Ik Song
IPC分类号： H05K1/16
CPC分类号： H05K1/162 , H01G4/105 , H01G4/33 , H05K2201/0175 , H05K2201/0179 , Y10T29/435
摘要： There is provided a thin film capacitor and a capacitor-embedded printed board improved in leakage current characteristics. A dielectric layer is formed of a BiZnNb-based amorphous metal oxide with a predetermined dielectric constant without being heat treated at a high temperature, and metallic phase bismuth of the BiZnNb-based amorphous metal oxide is adjusted in content to attain a desired dielectric constant. Also, another dielectric layer having a different content of metallic phase bismuth may be formed. The thin film capacitor including: a first electrode; a dielectric layer including a first dielectric film formed on the first electrode, the dielectric layer comprising a BiZnNb-based amorphous metal oxide; and a second electrode formed on the dielectric layer, wherein the BiZnNb-based amorphous metal oxide contains metallic phase bismuth.
摘要翻译：提供了薄膜电容器和电容器嵌入式印刷电路板，改善了漏电流特性。电介质层由具有预定介电常数的BiZnNb基非晶态金属氧化物形成，而不在高温下进行热处理，并且将BiZnNb基非晶态金属氧化物的金属相铋的含量调节到所需的介电常数。此外，可以形成具有不同金属相铋含量的另一介质层。所述薄膜电容器包括：第一电极; 介电层，包括形成在所述第一电极上的第一电介质膜，所述电介质层包含BiZnNb基非晶态金属氧化物; 以及形成在所述电介质层上的第二电极，其中所述BiZnNb基非晶态金属氧化物含有金属相铋。

6. 发明授权

US07737529B2 Printed circuit board with film capacitor embedded therein and method for manufacturing the same 有权
标题翻译：嵌入薄膜电容器的印刷电路板及其制造方法
公开(公告)号：US07737529B2
公开(公告)日：2010-06-15
申请号：US11582954
申请日：2006-10-19
申请人： Jin Seok Moon , Seung Eun Lee , Hyung Mi Jung , Yul Kyo Chung , Seung Hyun Sohn
发明人： Jin Seok Moon , Seung Eun Lee , Hyung Mi Jung , Yul Kyo Chung , Seung Hyun Sohn
IPC分类号： H01L29/00
CPC分类号： H05K1/162 , H05K3/388 , H05K2201/0175 , H05K2201/0179
摘要： The invention provides a PCB with a thin film capacitor embedded therein and a method for manufacturing the same. The PCB includes a lower electrode formed on an insulating substrate; an amorphous paraelectric film formed on the lower electrode via low temperature film formation; a buffer layer formed on the amorphous paraelectric film; a metal seed layer formed on the buffer layer; and an upper electrode formed on the metal seed layer.
摘要翻译：本发明提供一种其中嵌有薄膜电容器的PCB及其制造方法。 PCB包括形成在绝缘基板上的下电极; 通过低温成膜形成在下电极上的非晶顺电膜; 形成在所述非晶正电介质膜上的缓冲层; 形成在缓冲层上的金属种子层; 以及形成在金属籽晶层上的上电极。

7. 发明申请

US20080158777A1 Capacitor and multi-layer board embedding the capacitor 审中-公开
标题翻译：电容器和多层板嵌入电容器
公开(公告)号：US20080158777A1
公开(公告)日：2008-07-03
申请号：US11979770
申请日：2007-11-08
申请人： Seung Hyun Sohn , Yul Kyo Chung , Seung Eun Lee , Yee Na Shin
发明人： Seung Hyun Sohn , Yul Kyo Chung , Seung Eun Lee , Yee Na Shin
IPC分类号： H01G4/06 , H01G4/00
CPC分类号： H05K1/162 , H01G4/232 , H01G4/30 , H01G4/33 , H05K1/0231 , H05K1/185 , H05K3/4644 , H05K2201/0179 , H05K2201/09509 , H05K2201/09763 , H05K2201/09781
摘要： There are provided a capacitor and a thin film capacitor-embedded multi-layer wiring board. The capacitor includes: first and second electrodes connected to first and second polarities; a dielectric layer formed therebetween; and at least one floating electrode disposed inside the dielectric layer and having overlaps with the first and second electrodes. The wiring board includes: an insulating body having a plurality of insulating layers thereon; a plurality of conductive patterns and conductive vias formed on the insulating layers, respectively, to constitute an interlayer circuit; and a thin film capacitor embedded in the insulating body, wherein the thin film capacitor includes a first electrode layer, a first dielectric layer, at least one floating electrode layer, a second dielectric layer and a second electrode layer sequentially formed, and wherein the first and second electrode layers are connected to the interlayer circuit and the floating electrode layer is not directly connected thereto.
摘要翻译：提供电容器和薄膜电容器嵌入式多层布线板。电容器包括：连接到第一和第二极性的第一和第二电极; 在它们之间形成介电层; 以及至少一个浮置电极，其布置在电介质层的内部并与第一和第二电极重叠。布线板包括：绝缘体，其上具有多个绝缘层; 分别形成在绝缘层上的多个导电图案和导电通孔，以构成层间电路; 以及嵌入在所述绝缘体中的薄膜电容器，其中所述薄膜电容器包括依次形成的第一电极层，第一电介质层，至少一个浮置电极层，第二电介质层和第二电极层，并且其中所述第一电极层并且第二电极层连接到层间电路，并且浮动电极层不直接连接到其上。

8. 发明授权

US08513036B2 Photonic quantum ring laser and fabrication method thereof 失效
标题翻译：光子量子环激光器及其制造方法
公开(公告)号：US08513036B2
公开(公告)日：2013-08-20
申请号：US13524256
申请日：2012-06-15
申请人： O Dae Kwon , Mi-Hyang Shin , Seung Eun Lee , Young-Heub Jang , Young Chun Kim , Junho Yoon
发明人： O Dae Kwon , Mi-Hyang Shin , Seung Eun Lee , Young-Heub Jang , Young Chun Kim , Junho Yoon
IPC分类号： H01L21/00
CPC分类号： H01S5/34333 , B82Y20/00 , H01S5/0213 , H01S5/1075 , H01S5/1092 , H01S5/2027 , H01S5/2213 , H01S5/2214 , H01S5/2275 , H01S2304/04 , H04N9/315
摘要： A photonic quantum ring (PQR) laser includes an active layer having a multi-quantum-well (MQW) structure and etched lateral face. The active layer is formed to be sandwiched between p-GaN and n-GaN layers epitaxially grown on a reflector disposed over a support substrate. A coating layer is formed over an outside of the lateral faces of the active layer, and upper electrode is electrically connected to an upper portion of the n-GaN layer, and a distributed Bragg reflector (DBR) is formed over the n-GaN layer and the upper electrode. Accordingly, the PQR laser is capable of oscillating a power-saving vertically dominant 3D multi-mode laser suitable for a low power display device, prevent the light speckle phenomenon, and generate focus-adjusted 3D soft light.
摘要翻译：光子量子环（PQR）激光器包括具有多量子阱（MQW）结构和蚀刻的侧面的有源层。有源层形成为夹在p-GaN和外延生长在设置在支撑衬底上的反射器上的n-GaN层之间。在有源层的侧面的外侧形成涂层，上部电极与n-GaN层的上部电连接，在n-GaN层上形成分布式布拉格反射体（DBR）和上电极。因此，PQR激光器能够振荡适用于低功率显示装置的省电垂直显示3D多模激光器，防止光斑现象，并产生聚焦调整的3D软光。

9. 发明授权

US07736397B2 Method for manufacturing capacitor embedded in PCB 失效
标题翻译：制造电容器嵌入PCB的方法
公开(公告)号：US07736397B2
公开(公告)日：2010-06-15
申请号：US11730979
申请日：2007-04-05
申请人： Seung Eun Lee , Yul Kyo Chung , Hyung Dong Kang , Hyun Ju Jin
发明人： Seung Eun Lee , Yul Kyo Chung , Hyung Dong Kang , Hyun Ju Jin
IPC分类号： H01L21/8242 , H01G9/00
CPC分类号： H04R19/00 , H05K1/162 , H05K2201/0175 , H05K2201/0179 , H05K2201/0355 , H05K2201/09309 , H05K2203/0346 , H05K2203/0353 , Y10T29/417 , Y10T29/42 , Y10T29/43 , Y10T29/435
摘要： A method for manufacturing a capacitor embedded in a PCB includes: preparing a copper clad lamination (CCL) substrate having a reinforcement member and copper foils formed on both surfaces of the reinforcement member; planarizing surfaces of the copper foils of the CCL substrate; forming a dielectric layer on the planarized surface of the copper foils; and forming a top electrode on the dielectric layer.
摘要翻译：一种嵌入在PCB中的电容器的制造方法，其特征在于，包括：具有加强部件的铜包层压（CCL）基板和形成在所述加强部件的两面上的铜箔; 平坦化CCL基板的铜箔表面; 在铜箔的平坦化表面上形成电介质层; 并在电介质层上形成顶部电极。

10. 发明申请

US20080236878A1 Thin film capacitor, thin film capacitor-embedded printed circuit board and manufacturing method of thin film capacitor 有权
标题翻译：薄膜电容器，薄膜电容器嵌入式印刷电路板以及薄膜电容器的制造方法
公开(公告)号：US20080236878A1
公开(公告)日：2008-10-02
申请号：US12076989
申请日：2008-03-26
申请人： Seung Eun Lee , Yul Kyo Chung , Jung Won Lee , In Hyung Lee , Byung Ik Song
发明人： Seung Eun Lee , Yul Kyo Chung , Jung Won Lee , In Hyung Lee , Byung Ik Song
IPC分类号： H05K1/18 , H01G4/10 , H01G7/00
CPC分类号： H05K1/162 , H01G4/105 , H01G4/33 , H05K2201/0175 , H05K2201/0179 , Y10T29/435
摘要： There is provided a thin film capacitor and a capacitor-embedded printed board improved in leakage current characteristics. A dielectric layer is formed of a BiZnNb-based amorphous metal oxide with a predetermined dielectric constant without being heat treated at a high temperature, and metallic phase bismuth of the BiZnNb-based amorphous metal oxide is adjusted in content to attain a desired dielectric constant. Also, another dielectric layer having a different content of metallic phase bismuth may be formed. The thin film capacitor including: a first electrode; a dielectric layer including a first dielectric film formed on the first electrode, the dielectric layer comprising a BiZnNb-based amorphous metal oxide; and a second electrode formed on the dielectric layer, wherein the BiZnNb-based amorphous metal oxide contains metallic phase bismuth.
摘要翻译：提供了薄膜电容器和电容器嵌入式印刷电路板，改善了漏电流特性。电介质层由具有预定介电常数的BiZnNb基非晶态金属氧化物形成，而不在高温下进行热处理，并且将BiZnNb基非晶态金属氧化物的金属相铋的含量调节到所需的介电常数。此外，可以形成具有不同金属相铋含量的另一介质层。所述薄膜电容器包括：第一电极; 介电层，包括形成在所述第一电极上的第一电介质膜，所述电介质层包含BiZnNb基非晶态金属氧化物; 以及形成在所述电介质层上的第二电极，其中所述BiZnNb基非晶态金属氧化物含有金属相铋。

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