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1. 发明授权

US08631207B2 Cache memory power reduction techniques 有权
标题翻译：高速缓存存储器功耗缩减技术
公开(公告)号：US08631207B2
公开(公告)日：2014-01-14
申请号：US12647461
申请日：2009-12-26
申请人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
发明人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
摘要翻译：描述了提供存储器（诸如高速缓存存储器）中的功耗降低的方法和装置。在一个实施例中，使用虚拟标签来确定是否访问缓存方式。虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。在另一个实施例中，可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。还描述了其它实施例。

2. 发明申请

US20110161595A1 CACHE MEMORY POWER REDUCTION TECHNIQUES 有权
标题翻译：缓存记忆功率降低技术
公开(公告)号：US20110161595A1
公开(公告)日：2011-06-30
申请号：US12647461
申请日：2009-12-26
申请人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
发明人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
IPC分类号： G06F12/08 , G06F12/00 , G06F1/32
CPC分类号： G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
摘要翻译：描述了提供存储器（诸如高速缓存存储器）中的功耗降低的方法和装置。在一个实施例中，使用虚拟标签来确定是否访问缓存方式。虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。在另一个实施例中，可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。还描述了其它实施例。

3. 发明授权

US08621149B2 Controlling access to a cache memory using privilege level information 有权
标题翻译：使用特权级别信息控制对高速缓存的访问
公开(公告)号：US08621149B2
公开(公告)日：2013-12-31
申请号：US12645788
申请日：2009-12-23
申请人： Zhen Fang , Li Zhao , Ravishankar Iyer , Tong Li , Donald K. Newell
发明人： Zhen Fang , Li Zhao , Ravishankar Iyer , Tong Li , Donald K. Newell
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0895 , G06F12/1491 , Y02D10/13
摘要： In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，高速缓冲存储器包括各自存储环电平标识符的条目，其可以指示存储在条目中的信息的权限级别。该标识符可用于执行对高速缓冲存储器的读取访问。作为示例，耦合到高速缓存存储器的逻辑可以至少部分地基于处理器的当前特权级别和一个或多个高速缓冲存储器的环电平标识符来过滤对所选择的高速缓冲存储器组的一种或多种方式的访问，更多的方式描述和要求保护其他实施例。

4. 发明申请

US20120191896A1 CIRCUITRY TO SELECT, AT LEAST IN PART, AT LEAST ONE MEMORY 审中-公开
标题翻译：电路选择，至少一部分，至少一个记忆
公开(公告)号：US20120191896A1
公开(公告)日：2012-07-26
申请号：US13013104
申请日：2011-01-25
申请人： Zhen Fang , Li Zhao , Ravishankar Iyer , Srihari Makineni , Guangdeng Liao
发明人： Zhen Fang , Li Zhao , Ravishankar Iyer , Srihari Makineni , Guangdeng Liao
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , Y02D10/13
摘要： An embodiment may include circuitry to select, at least in part, from a plurality of memories, at least one memory to store data. The memories may be associated with respective processor cores. The circuitry may select, at least in part, the at least one memory based at least in part upon whether the data is included in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores. If the data is included in the at least one page, the circuitry may select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores. Many alternatives, variations, and modifications are possible.
摘要翻译：一个实施例可以包括至少部分地从多个存储器中选择至少一个存储器来存储数据的电路。存储器可以与相应的处理器核心相关联。该电路至少部分地至少部分地选择至少一个存储器，该至少一个存储器至少部分地基于是否将数据包括在跨越由至少一个处理器核处理的多个存储器线的至少一个页面中。如果数据被包括在至少一个页面中，则电路可以至少部分地选择至少一个存储器，使得至少一个存储器靠近处理器核心中的至少一个。许多替代方案，变化和修改是可能的。

5. 发明申请

US20110153926A1 Controlling Access To A Cache Memory Using Privilege Level Information 有权
标题翻译：控制使用特权级别信息访问缓存内存
公开(公告)号：US20110153926A1
公开(公告)日：2011-06-23
申请号：US12645788
申请日：2009-12-23
申请人： Zhen Fang , Li Zhao , Ravishankar Iyer , Tong Li , Donald K. Newell
发明人： Zhen Fang , Li Zhao , Ravishankar Iyer , Tong Li , Donald K. Newell
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0895 , G06F12/1491 , Y02D10/13
摘要： In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，高速缓冲存储器包括各自存储环电平标识符的条目，其可以指示存储在条目中的信息的权限级别。该标识符可用于执行对高速缓冲存储器的读取访问。作为示例，耦合到高速缓存存储器的逻辑可以至少部分地基于处理器的当前特权级别和一个或多个高速缓冲存储器的环电平标识符来过滤对所选择的高速缓冲存储器组的一种或多种方式的访问，更多的方式描述和要求保护其他实施例。

6. 发明授权

US09268611B2 Application scheduling in heterogeneous multiprocessor computing platform based on a ratio of predicted performance of processor cores 有权
标题翻译：基于处理器核心预测性能比例的异构多处理器计算平台中的应用调度
公开(公告)号：US09268611B2
公开(公告)日：2016-02-23
申请号：US12890653
申请日：2010-09-25
申请人： Ravishankar Iyer , Sadagopan Srinivasan , Li Zhao , Rameshkumar G. Illikkal
发明人： Ravishankar Iyer , Sadagopan Srinivasan , Li Zhao , Rameshkumar G. Illikkal
IPC分类号： G06F9/50 , G06F11/34 , G06F12/08
CPC分类号： G06F9/4881 , G06F9/5027 , G06F11/3409 , G06F11/3433 , G06F12/084 , G06F2201/88 , G06N5/02 , Y02D10/13 , Y02D10/22 , Y02D10/34
摘要： Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.
摘要翻译：描述了在异构多处理器计算平台中调度应用程序的方法和装置。在一个实施例中，处理器的多个处理器核的性能（例如，执行性能和/或功耗性能）的信息被存储（并被跟踪）在计数器和/或表中。处理器中的逻辑根据存储的信息确定哪个处理器内核应该执行应用程序。还要求和公开其它实施例。

7. 发明申请

US20110087843A1 Monitoring cache usage in a distributed shared cache 有权
标题翻译：监控分布式共享缓存中的缓存使用情况
公开(公告)号：US20110087843A1
公开(公告)日：2011-04-14
申请号：US12587670
申请日：2009-10-09
申请人： Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
发明人： Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864
摘要： An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.
摘要翻译：公开了一种装置，方法和系统。在一个实施例中，该装置包括多个组的高速缓冲存储器。高速缓冲存储器中的每个集合具有多个高速缓存行。该装置还包括至少一个进程资源表。进程资源表维护多个高速缓存行的高速缓存行占用数。具体地说，每个高速缓存行的高速缓存线占用率表示高速缓存存储由计算机系统上运行的进程使用的信息的高速缓存行数。此外，处理资源表存储比高速缓冲存储器中的高速缓存行总数少的高速缓存行的占用数。

8. 发明申请

US20080059707A1 Selective storage of data in levels of a cache memory 失效
标题翻译：在高速缓冲存储器的级别中选择性地存储数据
公开(公告)号：US20080059707A1
公开(公告)日：2008-03-06
申请号：US11513554
申请日：2006-08-31
申请人： Srihari Makineni , Jaideep Moses , Ravishankar Iyer , Ramesh Illikkal , Don Newell , Li Zhao
发明人： Srihari Makineni , Jaideep Moses , Ravishankar Iyer , Ramesh Illikkal , Don Newell , Li Zhao
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/128
摘要： In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the cache line into a second level cache coupled to the first level cache or a third level cache coupled to the second level cache based on the counter value, after eviction from the first level cache. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在高速缓存行插入到第一级高速缓存中时递增与高速缓存线相关联的计数器值的方法，并且将高速缓存行存储到耦合到第一级高速缓存的第二级高速缓存或在从第一级高速缓存驱逐之后，基于计数器值耦合到第二级高速缓存的第三级缓存。描述和要求保护其他实施例。

9. 发明申请

US20080040554A1 Providing quality of service (QoS) for cache architectures using priority information 有权
标题翻译：使用优先级信息为缓存架构提供服务质量（QoS）
公开(公告)号：US20080040554A1
公开(公告)日：2008-02-14
申请号：US11503633
申请日：2006-08-14
申请人： Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell
发明人： Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell
IPC分类号： G06F13/00
CPC分类号： G06F12/126
摘要： In one embodiment, the present invention includes a method for associating a first priority indicator with first data stored in a first entry of a cache memory to indicate a priority level of the first data, and updating a count value associated with the first priority indicator. The count value may then be used in determining an appropriate cache line for eviction. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于将第一优先级指示符与存储在高速缓冲存储器的第一条目中的第一数据相关联以指示第一数据的优先级，以及更新与第一优先级指示符相关联的计数值的方法。然后可以将计数值用于确定用于驱逐的适当的高速缓存行。描述和要求保护其他实施例。

10. 发明授权

US07802057B2 Priority aware selective cache allocation 有权
标题翻译：优先级识别选择性缓存分配
公开(公告)号：US07802057B2
公开(公告)日：2010-09-21
申请号：US11965131
申请日：2007-12-27
申请人： Ravishankar Iyer , Ramesh Milekal , Donald Newell , Li Zhao
发明人： Ravishankar Iyer , Ramesh Milekal , Donald Newell , Li Zhao
IPC分类号： G06F12/06 , G06F9/50
CPC分类号： G06F12/126 , G06F9/5016 , G06F12/0888
摘要： A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation probabilities for each priority level are updated based on the measured consumption/utilization, i.e. allocation is reduced for priority levels consuming too much of the cache and allocation is increased for priority levels consuming too little of the cache. In response to an allocation request, it is assigned a priority level. An allocation probability associated with the priority level is compared with a randomly generated number. If the number is less than the allocation probability, then a fill to the cache is performed normally. In contrast, a spatially or temporally limited fill is performed if the random number is greater than the allocation probability.
摘要翻译：本文描述了提供高速缓冲存储器的优先级感知和消耗引导的动态概率分配的方法和装置。针对计算机系统的每个优先级测量利用高速缓冲存储器的样本大小。基于所测量的消耗/利用率来更新每个优先级的分配概率，即对于消耗太多高速缓存的优先级降低了分配，并且对于消耗太多缓存的优先级来说，分配增加。响应于分配请求，它被分配优先级。将与优先级相关联的分配概率与随机生成的数字进行比较。如果该数量小于分配概率，则正常地执行对高速缓存的填充。相比之下，如果随机数大于分配概率，则执行空间或时间有限的填充。

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