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51. 发明申请

US20140138744A1 TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS 有权
标题翻译：用于CMOS结构的隧道场效应晶体管（TFET）和制造N型和P型TFETS的方法
公开(公告)号：US20140138744A1
公开(公告)日：2014-05-22
申请号：US13678867
申请日：2012-11-16
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/78
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
摘要翻译：描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。栅极堆叠包括栅极电介质部分和栅极电极部分。

52. 发明申请

US20140035059A1 SEMICONDUCTOR DEVICE HAVING METALLIC SOURCE AND DRAIN REGIONS 有权
标题翻译：具有金属源和漏区的半导体器件
公开(公告)号：US20140035059A1
公开(公告)日：2014-02-06
申请号：US13995419
申请日：2011-12-19
申请人： Martin D. Giles , Annalisa Cappellani , Sanaz Kabehie , Rafael Rios , Cory E. Weber , Aaron A. Budrevich
发明人： Martin D. Giles , Annalisa Cappellani , Sanaz Kabehie , Rafael Rios , Cory E. Weber , Aaron A. Budrevich
IPC分类号： H01L27/092 , H01L21/8238 , H01L27/088
CPC分类号： H01L29/7848 , H01L21/2225 , H01L21/2254 , H01L21/2257 , H01L21/2258 , H01L21/28518 , H01L21/28556 , H01L21/28593 , H01L21/30608 , H01L21/30617 , H01L21/3065 , H01L21/823814 , H01L21/823821 , H01L27/088 , H01L27/092 , H01L29/0673 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/401 , H01L29/456 , H01L29/66636 , H01L29/66795 , H01L29/7839 , H01L29/7845 , H01L29/785 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
摘要翻译：描述具有金属源极和漏极区域的半导体器件。例如，半导体器件包括设置在衬底的半导体沟道区域上方的栅电极堆叠。金属源区和漏区设置在衬底的上方，位于半导体沟道区的任一侧。金属源极和漏极区域中的每个具有轮廓。第一半导体外扩散区域设置在衬底中，在半导体沟道区域和金属源极区域之间，并与金属源极区域的形状保持一致。第二半导体外扩散区域设置在衬底中，在半导体沟道区域和金属漏极区域之间，并与金属漏极区域的轮廓保形。

53. 发明申请

US20140001441A1 INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES 有权
标题翻译：用于制造纳米器件的内部间隔件的集成方法
公开(公告)号：US20140001441A1
公开(公告)日：2014-01-02
申请号：US13539195
申请日：2012-06-29
申请人： Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Mark Armstrong , Rafael Rios , Abhijit Jayant Pethe , Willy Rachmady
发明人： Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Mark Armstrong , Rafael Rios , Abhijit Jayant Pethe , Willy Rachmady
IPC分类号： H01L29/78 , H01L21/336 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/0673 , B82Y40/00 , H01L21/30604 , H01L21/3105 , H01L21/31155 , H01L29/0847 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/78 , H01L29/78696
摘要： A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
摘要翻译：公开了一种具有多个内部间隔物的纳米线器件和用于形成所述内部间隔物的方法。在一个实施例中，半导体器件包括设置在衬底上方的纳米线堆叠，纳米线堆叠具有多个垂直堆叠的纳米线，围绕多个纳米线中的每一个缠绕的栅极结构，限定器件的沟道区，栅极结构，其具有栅极侧壁，在沟道区域的相对侧上的一对源极/漏极区域; 以及位于纳米线堆叠内部的两个相邻纳米线之间的栅极侧壁的一部分上的内部间隔物。在一个实施例中，内部间隔物通过在与沟道区相邻蚀刻的凹坑中沉积间隔物形成。在一个实施例中，通过沟道区蚀刻凹坑。在另一个实施例中，通过源/漏区蚀刻凹坑。

54. 发明申请

US20130334572A1 JUNCTIONLESS ACCUMULATION-MODE DEVICES ON DECOUPLED PROMINENT ARCHITECTURES 有权
标题翻译：关于解散的建筑结构的无连续累积模式设备
公开(公告)号：US20130334572A1
公开(公告)日：2013-12-19
申请号：US13964696
申请日：2013-08-12
申请人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar Mudanai
发明人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar Mudanai
IPC分类号： H01L29/205 , H01L29/78
CPC分类号： H01L29/775 , H01L29/0669 , H01L29/205 , H01L29/66439 , H01L29/66795 , H01L29/785 , H01L2029/7857
摘要： A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.
摘要翻译：通过在JAM半导体主体的突出特征之下的反向偏压带将无连接累积模式（JAM）半导体器件从半导体衬底隔离。制造JAM器件的过程包括植入和外延。

55. 发明授权

US08507948B2 Junctionless accumulation-mode devices on prominent architectures, and methods of making same 有权
标题翻译：突出架构上的无结点累加模式设备及其制作方法
公开(公告)号：US08507948B2
公开(公告)日：2013-08-13
申请号：US12978248
申请日：2010-12-23
申请人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar P. Mudanai
发明人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar P. Mudanai
IPC分类号： H01L29/66
CPC分类号： H01L29/775 , H01L29/0669 , H01L29/205 , H01L29/66439 , H01L29/66795 , H01L29/785 , H01L2029/7857
摘要： A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.
摘要翻译：无连接累积模式（JAM）半导体器件通过JAM半导体的突出特征之下的反向偏压带从半导体衬底隔离。制造JAM器件的过程包括植入和外延。

56. 发明申请

US20080237719A1 Multi-gate structure and method of doping same 审中-公开
标题翻译：多栅极结构及掺杂方法
公开(公告)号：US20080237719A1
公开(公告)日：2008-10-02
申请号：US11729198
申请日：2007-03-28
申请人： Brian S. Doyle , Suman Datta , Jack T. Kavalieros , Rafael Rios
发明人： Brian S. Doyle , Suman Datta , Jack T. Kavalieros , Rafael Rios
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803
摘要： A multi-gate structure includes a substrate (110, 210, 410), an electrically insulating layer (120, 220, 420) over the substrate, and a first semiconducting fin (130, 230, 430) above the electrically insulating layer. The first semiconducting fin includes a top region (131, 231, 431), a first side region (132, 232, 432), and a second side region (133, 233, 433). The top region, the first side region, and the second side region have doping concentrations that are substantially equal to each other. The multi-gate structure may be made by depositing a solid source material (510) over the semiconducting fin, and by annealing the multi-gate structure such that dopants from the solid source material diffuse into the semiconducting fin and uniformly dope the top region and the first and second side regions.
摘要翻译：多栅极结构包括衬底（110,210,410），在衬底上方的电绝缘层（120,220,420）以及在电绝缘层上方的第一半导电翅片（130,230,430）。第一半导体鳍片包括顶部区域（131,231,431），第一侧面区域（132,232,432）和第二侧面区域（133,233,433）。顶部区域，第一侧面区域和第二侧面区域具有彼此基本相等的掺杂浓度。多栅极结构可以通过在半导体鳍上沉积固体源材料（510）并且通过退火多栅极结构使得来自固体源材料的掺杂剂扩散到半导体翅片中并且均匀地掺杂顶部区域和第一和第二侧区域。

57. 发明授权

US07091560B2 Method and structure to decrease area capacitance within a buried insulator device 失效
标题翻译：降低埋层绝缘体内部面积电容的方法和结构
公开(公告)号：US07091560B2
公开(公告)日：2006-08-15
申请号：US10806609
申请日：2004-03-22
申请人： Mark A. Stettler , Borna Obradovic , Martin D. Giles , Rafael Rios
发明人： Mark A. Stettler , Borna Obradovic , Martin D. Giles , Rafael Rios
IPC分类号： H01L27/01 , H01L21/336
CPC分类号： B82Y10/00 , H01L29/66772 , H01L29/78603 , H01L29/78606
摘要： Method and structure to decrease area capacitance within a buried insulator device structure are disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.
摘要翻译：公开了减少掩埋绝缘体器件结构内的面积电容的方法和结构。与栅极的绝缘体层相对的掩埋绝缘体结构的衬底层的一部分掺杂有与器件的源极和漏极区相同的掺杂极性，以提供减小的面积电容。这种掺杂可以限于不在栅极下方的衬底的部分。

58. 发明申请

US20060046452A1 N-gate transistor 审中-公开
标题翻译： N栅晶体管
公开(公告)号：US20060046452A1
公开(公告)日：2006-03-02
申请号：US11208159
申请日：2005-08-19
申请人： Rafael Rios , Brian Doyle , Thomas Linton , Jack Kavalieros
发明人： Rafael Rios , Brian Doyle , Thomas Linton , Jack Kavalieros
IPC分类号： H01L21/3205
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A n-gate transistor, and method of forming such, including source/drain regions connected by a channel region and a gate electrode coupled to the channel region. The channel region has many angled edges protruding into the gate electrode. The many angled edges are to act as electrically conducting channel conduits between source/drain regions.
摘要翻译：一种n型栅极晶体管及其形成方法，包括由沟道区域连接的源极/漏极区域和耦合到沟道区域的栅电极。通道区域具有突出到栅电极中的许多成角度的边缘。许多成角度的边缘用作在源极/漏极区域之间的导电沟道导管。

59. 发明授权

US06960517B2 N-gate transistor 失效
标题翻译： N栅晶体管
公开(公告)号：US06960517B2
公开(公告)日：2005-11-01
申请号：US10610835
申请日：2003-06-30
申请人： Rafael Rios , Brian S. Doyle , Thomas D. Linton, Jr. , Jack Kavalieros
发明人： Rafael Rios , Brian S. Doyle , Thomas D. Linton, Jr. , Jack Kavalieros
IPC分类号： H01L21/336 , H01L29/786 , H01L21/3205
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A n-gate transistor, and method of forming such, including source/drain regions connected by a channel region and a gate electrode coupled to the channel region. The channel region has many angled edges protruding into the gate electrode. The many angled edges are to act as electrically conducting channel conduits between source/drain regions.
摘要翻译：一种n型栅极晶体管及其形成方法，包括由沟道区域连接的源极/漏极区域和耦合到沟道区域的栅电极。通道区域具有突出到栅电极中的许多成角度的边缘。许多成角度的边缘用作在源极/漏极区域之间的导电沟道导管。

60. 发明授权

US06867104B2 Method to form a structure to decrease area capacitance within a buried insulator device 失效
标题翻译：形成掩埋绝缘体器件中减小面积电容的结构的方法
公开(公告)号：US06867104B2
公开(公告)日：2005-03-15
申请号：US10334181
申请日：2002-12-28
申请人： Mark A. Stettler , Borna Obradovic , Martin D. Giles , Rafael Rios
发明人： Mark A. Stettler , Borna Obradovic , Martin D. Giles , Rafael Rios
IPC分类号： H01L21/336 , H01L27/01 , H01L27/12 , H01L29/786 , H01L31/0392
CPC分类号： B82Y10/00 , H01L29/66772 , H01L29/78603 , H01L29/78606
摘要： Method to form a structure to decrease area capacitance within a buried insulator device structure is disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.
摘要翻译：公开了一种形成掩埋绝缘体器件结构内减小面积电容的结构的方法。与栅极的绝缘体层相对的掩埋绝缘体结构的衬底层的一部分掺杂有与器件的源极和漏极区相同的掺杂极性，以提供减小的面积电容。这种掺杂可以限于不在栅极下方的衬底的部分。

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