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1. 发明申请

US20170084326A1 A NEGATIVE DIFFERENTIAL RESISTANCE BASED MEMORY 审中-公开
公开(公告)号：US20170084326A1
公开(公告)日：2017-03-23
申请号：US15126255
申请日：2014-07-08
申请人： Daniel H. Morris , Uygar E. Avci , Rafael Rios , Ian A. Young
发明人： Daniel H. Morris , Uygar E. Avci , Rafael Rios , Ian A. Young
IPC分类号： G11C11/38 , H01L27/105 , H01L27/102 , G11C11/412
CPC分类号： G11C11/38 , G11C11/404 , G11C11/412 , H01L27/102 , H01L27/1021 , H01L27/1052 , H01L29/7391 , H01L29/885
摘要： Described is a memory bit-cell comprising: a storage node; an access transistor coupled to the storage node; a capacitor having a first terminal coupled to the storage node; and one or more negative differential resistance devices coupled to the storage node such that the memory bit-cell is without one of a ground line or a supply line or both.

2. 发明申请

US20160182023A1 APPARATUSES, METHODS, AND SYSTEMS FOR DENSE CIRCUITRY USING TUNNEL FIELD EFFECT TRANSISTORS 有权
标题翻译：使用隧道场效应晶体管的DENSE电路的装置，方法和系统
公开(公告)号：US20160182023A1
公开(公告)日：2016-06-23
申请号：US14575962
申请日：2014-12-18
申请人： Daniel H. Morris , Uygar E. Avci , Rafael Rios , Ian A. Young
发明人： Daniel H. Morris , Uygar E. Avci , Rafael Rios , Ian A. Young
IPC分类号： H03K3/356 , G11C11/419
CPC分类号： G11C11/419 , G11C5/145 , G11C11/412 , H01L27/1104 , H03K3/356104
摘要： Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal. The circuit may further include a second transistor coupled to receive the low voltage signal from the second inverter to serve as a feedback device and produce a high voltage signal. In embodiments, the first transistor conducts asymmetrically to prevent crossover of the high voltage signal into the low voltage domain. A low voltage memory array is also described. In embodiments, the circuit to shift a voltage level may assist communication between a logic component including the low voltage memory array of a low voltage domain and a logic component of a high voltage domain. Additional embodiments may also be described.
摘要翻译：实施例包括用于移位电压电平的电路的装置，方法和系统。电路可以包括第一反相器，其包括耦合以传递低电压信号的第一晶体管和耦合以接收低电压信号的第二反相器。电路还可以包括第二晶体管，其被耦合以从第二反相器接收低电压信号，以用作反馈装置并产生高电压信号。在实施例中，第一晶体管不对称地导通，以防止高电压信号到低电压域的交叉。还描述了低电压存储器阵列。在实施例中，用于移位电压电平的电路可以有助于包括低电压域的低电压存储器阵列和高电压域的逻辑分量的逻辑组件之间的通信。还可以描述另外的实施例。

3. 发明授权

US08890120B2 Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs 有权
标题翻译：用于CMOS方法的隧道场效应晶体管（TFET）用于制造N型和P型TFET
公开(公告)号：US08890120B2
公开(公告)日：2014-11-18
申请号：US13678867
申请日：2012-11-16
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
摘要翻译：描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。栅极堆叠包括栅极电介质部分和栅极电极部分。

4. 发明申请

US20150041847A1 TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS 审中-公开
标题翻译：用于CMOS结构的隧道场效应晶体管（TFET）和制造N型和P型TFETS的方法
公开(公告)号：US20150041847A1
公开(公告)日：2015-02-12
申请号：US14521200
申请日：2014-10-22
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/78 , H01L29/267 , H01L29/06 , H01L29/24 , H01L29/16
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
摘要翻译：描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。栅极堆叠包括栅极电介质部分和栅极电极部分。

5. 发明申请

US20140138744A1 TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS 有权
标题翻译：用于CMOS结构的隧道场效应晶体管（TFET）和制造N型和P型TFETS的方法
公开(公告)号：US20140138744A1
公开(公告)日：2014-05-22
申请号：US13678867
申请日：2012-11-16
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/78
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
摘要翻译：描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。栅极堆叠包括栅极电介质部分和栅极电极部分。

6. 发明授权

US09583602B2 Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs 有权
标题翻译：用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法
公开(公告)号：US09583602B2
公开(公告)日：2017-02-28
申请号：US15209552
申请日：2016-07-13
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/66 , H01L29/78 , H01L29/739 , H01L29/16 , H01L29/161 , H01L29/06 , H01L29/24 , H01L29/267 , H01L27/092 , H01L29/04 , H01L29/10 , H01L29/165 , H01L29/20 , H01L29/423 , H01L29/786
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
摘要翻译：描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。栅极堆叠包括栅极电介质部分和栅极电极部分。

7. 发明申请

US20160322480A1 TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS 审中-公开
公开(公告)号：US20160322480A1
公开(公告)日：2016-11-03
申请号：US15209552
申请日：2016-07-13
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/66 , H01L29/06 , H01L29/165 , H01L27/092 , H01L29/161 , H01L29/10 , H01L29/20 , H01L29/04 , H01L29/786 , H01L29/423
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

8. 发明授权

US09362074B2 Nanowire-based mechanical switching device 有权
标题翻译：基于纳米线的机械开关装置
公开(公告)号：US09362074B2
公开(公告)日：2016-06-07
申请号：US13996507
申请日：2013-03-14
申请人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
发明人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
IPC分类号： H01H51/22 , H01H59/00 , B82Y10/00 , H01H1/00 , H01H9/02
CPC分类号： H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
摘要翻译：描述了基于纳米线的机械开关装置。例如，纳米线继电器包括布置在衬底上方的空隙中的纳米线。纳米线具有锚固部分和悬挂部分。第一栅电极邻近空隙设置，并与纳米线隔开。第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线隔开。

9. 发明申请

US20160329438A1 NANOWIRE-BASED MECHANICAL SWITCHING DEVICE 有权
标题翻译：基于纳米级的机械开关装置
公开(公告)号：US20160329438A1
公开(公告)日：2016-11-10
申请号：US15151381
申请日：2016-05-10
申请人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
发明人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
IPC分类号： H01L29/84 , H01H59/00 , H01L29/161 , H01L29/06 , H01L29/04
CPC分类号： H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
摘要翻译：描述了基于纳米线的机械开关装置。例如，纳米线继电器包括布置在衬底上方的空隙中的纳米线。纳米线具有锚固部分和悬挂部分。第一栅电极邻近空隙设置，并与纳米线隔开。第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线隔开。

10. 发明申请

US20140262707A1 NANOWIRE-BASED MECHANICAL SWITCHING DEVICE 有权
标题翻译：基于纳米级的机械开关装置
公开(公告)号：US20140262707A1
公开(公告)日：2014-09-18
申请号：US13996507
申请日：2013-03-14
申请人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
发明人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
IPC分类号： H01H59/00
CPC分类号： H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
摘要翻译：描述了基于纳米线的机械开关装置。例如，纳米线继电器包括布置在衬底上方的空隙中的纳米线。纳米线具有锚固部分和悬挂部分。第一栅电极邻近空隙设置，并与纳米线隔开。第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线隔开。

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