专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130018499A1 PRODUCIBILITY ANALYSIS DURING ENGINEERING DESIGN OF COMPOSITE PARTS 审中-公开
标题翻译：复合材料工程设计中的可生产性分析
公开(公告)号：US20130018499A1
公开(公告)日：2013-01-17
申请号：US13267878
申请日：2011-10-06
申请人： Jeffrey L. Miller , Stephen J. Dostert
发明人： Jeffrey L. Miller , Stephen J. Dostert
IPC分类号： G06F19/00
CPC分类号： B29C70/54 , B64F5/40
摘要： A method comprises using a computer to access an engineering definition of a composite part and apply a set of rules governing material laydown prior to performing the laydown.
摘要翻译：一种方法包括使用计算机来访问复合部件的工程定义，并且在执行放置之前应用一组管理材料沉积的规则。

2. 发明申请

US20130014378A1 Cell including clean and dirty sections for fabricating composite parts 有权
标题翻译：电池包括用于制造复合零件的干净和脏的部分
公开(公告)号：US20130014378A1
公开(公告)日：2013-01-17
申请号：US13267876
申请日：2011-10-06
申请人： Jeffrey L. Miller
发明人： Jeffrey L. Miller
IPC分类号： B23P17/04 , B65G47/74 , B23P23/04
CPC分类号： B29C73/04 , B29C35/02 , B29C35/0227 , B29C70/00 , B29C70/30 , B29C70/32 , Y02T50/43 , Y10T29/49 , Y10T29/49801 , Y10T29/49995 , Y10T29/51
摘要： A cell for fabricating a part having reinforcing fibers embedded in a matrix, includes a clean section for performing clean operations including laying up the reinforcing fibers on a mandrel tool. The clean section satisfies clean room requirements for processing uncured composite materials. The cell further includes an adjacent dirty section for performing dirty operations including machining the layup after curing; a common end effector positioning system movable between the clean and dirty sections; and means for preventing contaminants in the dirty section from entering the clean section.
摘要翻译：用于制造具有嵌入基体中的增强纤维的部件的电池包括用于执行清洁操作的清洁部分，包括将加强纤维铺设在心轴工具上。清洁部分满足对未固化复合材料加工的洁净室要求。电池还包括相邻的脏部分，用于执行脏操作，包括在固化之后加工叠层; 一个共同的末端执行器定位系统，可在清洁和脏的部分之间移动; 以及用于防止脏部分中的污染物进入清洁部分的装置。

3. 发明授权

US07345947B2 Memory array leakage reduction circuit and method 有权
标题翻译：存储阵列泄漏减少电路及方法
公开(公告)号：US07345947B2
公开(公告)日：2008-03-18
申请号：US11516209
申请日：2006-09-05
申请人： Jeffrey L. Miller , Mahadevamurty Nemani , James W. Conary
发明人： Jeffrey L. Miller , Mahadevamurty Nemani , James W. Conary
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/413
摘要： Embodiments of the invention provide techniques for reducing standby power consumption due to leakage currents in memory circuits. In some embodiments, systems are provided with one or more processors having) bit cells coupled to a word-line node and to a virtual ground node. The word-line node is to be at an active word-line voltage when the row is active and an inactive word-line voltage when the row is inactive. The virtual ground node is to be at an operational ground voltage when the memory array is enabled and at an elevated voltage when the memory array is in a standby mode. There is also a word-line driver circuit coupled to the bit cells through the word-line and virtual ground nodes. The current leakage in the bit cells and word-line driver circuit is reduced during the standby mode when the virtual ground node is at the elevated voltage.
摘要翻译：本发明的实施例提供了用于减少由于存储器电路中的漏电流引起的待机功耗的技术。在一些实施例中，系统具有一个或多个处理器，其具有耦合到字线节点和虚拟接地节点的位单元。当行处于活动状态时，字线节点将处于活动字线电压，而当行处于非活动状态时，字线节点处于活动字线电压。当存储器阵列被使能并且当存储器阵列处于待机模式时处于升高的电压时，虚拟接地节点将处于操作接地电压。还有通过字线和虚拟接地节点耦合到位单元的字线驱动电路。当虚拟接地节点处于升高的电压时，在待机模式期间，位单元和字线驱动电路中的电流泄漏减小。

4. 发明授权

US07164616B2 Memory array leakage reduction circuit and method 有权
标题翻译：存储阵列泄漏减少电路及方法
公开(公告)号：US07164616B2
公开(公告)日：2007-01-16
申请号：US11018013
申请日：2004-12-20
申请人： Jeffrey L. Miller , Mahadevamurty Nemani , James W. Conary
发明人： Jeffrey L. Miller , Mahadevamurty Nemani , James W. Conary
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/413
摘要： Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory array circuits.
摘要翻译：这里公开了用于减少由于存储器阵列电路中的漏电流引起的待机功耗的技术。

5. 发明授权

US06175928B1 Reducing timing variance of signals from an electronic device 失效
标题翻译：降低来自电子设备的信号的时序变化
公开(公告)号：US06175928B1
公开(公告)日：2001-01-16
申请号：US09002019
申请日：1997-12-31
申请人： Jonathan H. Liu , Michael J. Allen , James W. Conary , David P. DiMarco , Jeffrey L. Miller
发明人： Jonathan H. Liu , Michael J. Allen , James W. Conary , David P. DiMarco , Jeffrey L. Miller
IPC分类号： G06F104
CPC分类号： G06F1/14 , G06F1/04
摘要： A time delay from a triggering event to switching of an output signal in a microelectronic device can be adjusted to compensate for various characteristics of the electronic device. The characteristics include temperature, voltage, and manufacturing process conditions. The time delay is adjusted using a variable delay circuit having multiple delay cells that are selectively coupled to control the time delay. The conditions of the electronic device are detected using a process sensor, which includes an oscillator having a frequency that is sensitive to variations in the conditions.
摘要翻译：可以调整从触发事件到微电子器件中的输出信号切换的时间延迟以补偿电子设备的各种特性。特性包括温度，电压和制造工艺条件。使用具有选择性耦合以控制时间延迟的多个延迟单元的可变延迟电路来调整时间延迟。使用处理传感器检测电子设备的状况，该过程传感器包括具有对条件变化敏感的频率的振荡器。

6. 发明授权

US09336156B2 Method and apparatus for cache line state update in sectored cache with line state tracker 有权
标题翻译：线路状态跟踪器的扇区高速缓存行状态更新方法和装置
公开(公告)号：US09336156B2
公开(公告)日：2016-05-10
申请号：US13827271
申请日：2013-03-14
申请人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
发明人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F12/0826 , G06F12/0864 , G06F12/0895 , G06F2212/60
摘要： A processing device and method for cache control including tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, a cache controller of the processing device can perform one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array. The cache controller can track pending line state updates to a superline outside of the tag array, and a line state update can occur in the cache controller, rather than awaiting completion of all outstanding operations on a superline. Updates to multiple line states can be maintained simultaneously, and up-to-date ECCs computed.
摘要翻译：描述了用于高速缓存控制的处理设备和方法，包括跟踪对高速缓存超线程的线路状态的更新。响应于与超级线相关的请求，处理设备的高速缓存控制器可以执行一个或多个读 - 修改 - 写入（RMW）操作，以（a）线状态阵列的线状态向量和（b）计数器的行状态数组。基于对超线程的一个或多个请求已经完成的确定，来自线状态阵列的线状态向量可以被写入标签阵列。高速缓存控制器可以跟踪到标签阵列之外的超级线路的待处理线路状态更新，并且线路状态更新可能发生在高速缓存控制器中，而不是等待完成超级线上所有未完成的操作。可以同时维护对多行状态的更新，并计算最新的ECC。

7. 发明申请

US20140281251A1 METHOD AND APPARATUS FOR CACHE LINE STATE UPDATE IN SECTORED CACHE WITH LINE STATE TRACKER 有权
标题翻译：使用线状跟踪器在高速缓存中缓存线状态更新的方法和装置
公开(公告)号：US20140281251A1
公开(公告)日：2014-09-18
申请号：US13827271
申请日：2013-03-14
申请人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
发明人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F12/0826 , G06F12/0864 , G06F12/0895 , G06F2212/60
摘要： Technologies for tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array can be performed. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array.
摘要翻译：描述了用于跟踪对高速缓存超级线路的线路状态的更新的技术。响应于关于超级线的请求，可以执行一个或多个读 - 修改 - 写入（RMW）操作，以（a）线状态阵列的线状态向量和（b）行状态阵列的计数器。基于对超线程的一个或多个请求已经完成的确定，来自线状态阵列的线状态向量可以被写入标签阵列。

8. 发明申请

US20130014889A1 RAPID FABRICATION OF A COMPOSITE PART 有权
标题翻译：复合零件的快速制造
公开(公告)号：US20130014889A1
公开(公告)日：2013-01-17
申请号：US13291083
申请日：2011-11-07
申请人： Jeffrey L. Miller , Stephen J. Dostert , Michael J. Louderback
发明人： Jeffrey L. Miller , Stephen J. Dostert , Michael J. Louderback
IPC分类号： B32B38/10 , B32B37/14 , B32B38/00
CPC分类号： B32B38/10 , B29C33/3842 , B29C33/40 , B29C70/30 , Y10T156/1052 , Y10T156/1348 , Y10T156/1795
摘要： A method of fabricating a composite part including reinforcing fibers comprises fabricating a masterless layup mandrel tool at a fabrication site. The tool includes a composite face sheet that provides a layup surface. The method further comprises using the masterless tool at that site to form a layup of the reinforcing fibers.
摘要翻译：一种制造包括增强纤维的复合材料部件的方法包括在制造部位制造无主覆层心轴工具。该工具包括提供铺设表面的复合面板。该方法还包括在该位置使用无主工具以形成增强纤维的叠层。

9. 发明授权

US06198983B1 Table-driven software architecture for a stitching system 失效
标题翻译：用于拼接系统的表驱动软件架构
公开(公告)号：US06198983B1
公开(公告)日：2001-03-06
申请号：US08995843
申请日：1997-12-22
申请人： Patrick J. Thrash , Jeffrey L. Miller , Ken Pallas , Robert C. Trank , Rhoda Fox , Mike Korte , Richard Codos , Alexandre Korolev , William Collan
发明人： Patrick J. Thrash , Jeffrey L. Miller , Ken Pallas , Robert C. Trank , Rhoda Fox , Mike Korte , Richard Codos , Alexandre Korolev , William Collan
IPC分类号： D05C502
CPC分类号： D05B19/08 , D05B23/00
摘要： Native code for a CNC stitching machine is generated by generating a geometry model of a preform; generating tool paths from the geometry model, the tool paths including stitching instructions for making stitches; and generating additional instructions indicating thickness values. The thickness values are obtained from a lookup table. When the stitching machine runs the native code, it accesses a lookup table to determine a thread tension value corresponding to the thickness value. The stitching machine accesses another lookup table to determine a thread path geometry value corresponding to the thickness value.
摘要翻译：通过生成预成型件的几何模型来生成CNC拼接机的本地代码; 从所述几何模型生成工具路径，所述刀具路径包括用于制作针迹的缝合指令; 并产生指示厚度值的附加指令。厚度值从查找表获得。当缝纫机运行本地代码时，它访问查找表以确定与厚度值对应的线张力值。缝合机访问另一查找表以确定对应于厚度值的线程几何值。

10. 发明授权

US06172546B2 Method and apparatus to monitor a characteristic associated with an electronic device 有权
标题翻译：监测与电子设备相关的特性的方法和装置
公开(公告)号：US06172546B2
公开(公告)日：2001-01-09
申请号：US09415682
申请日：1999-10-08
申请人： Jonathan H. Liu , Michael J. Allen , James W. Conary , David P. DiMarco , Jeffrey L. Miller
发明人： Jonathan H. Liu , Michael J. Allen , James W. Conary , David P. DiMarco , Jeffrey L. Miller
IPC分类号： H03H1126
CPC分类号： G06F1/14 , G06F1/04
摘要： A time delay from a triggering event to switching of an output signal in a microelectronic device can be adjusted to compensate for various characteristics of the electronic device. The characteristics include temperature, voltage, and manufacturing process conditions. The time delay is adjusted using a variable delay circuit having multiple delay cells that are selectively coupled to control the time delay. The conditions of the electronic device are detected using a process sensor, which includes an oscillator having a frequency that is sensitive to variations in the conditions.
摘要翻译：可以调整从触发事件到微电子器件中的输出信号切换的时间延迟以补偿电子设备的各种特性。特性包括温度，电压和制造工艺条件。使用具有选择性耦合以控制时间延迟的多个延迟单元的可变延迟电路来调整时间延迟。使用处理传感器检测电子设备的状况，该过程传感器包括具有对条件变化敏感的频率的振荡器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式