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1. 发明授权

US09336156B2 Method and apparatus for cache line state update in sectored cache with line state tracker 有权
标题翻译：线路状态跟踪器的扇区高速缓存行状态更新方法和装置
公开(公告)号：US09336156B2
公开(公告)日：2016-05-10
申请号：US13827271
申请日：2013-03-14
申请人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
发明人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F12/0826 , G06F12/0864 , G06F12/0895 , G06F2212/60
摘要： A processing device and method for cache control including tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, a cache controller of the processing device can perform one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array. The cache controller can track pending line state updates to a superline outside of the tag array, and a line state update can occur in the cache controller, rather than awaiting completion of all outstanding operations on a superline. Updates to multiple line states can be maintained simultaneously, and up-to-date ECCs computed.
摘要翻译：描述了用于高速缓存控制的处理设备和方法，包括跟踪对高速缓存超线程的线路状态的更新。响应于与超级线相关的请求，处理设备的高速缓存控制器可以执行一个或多个读 - 修改 - 写入（RMW）操作，以（a）线状态阵列的线状态向量和（b）计数器的行状态数组。基于对超线程的一个或多个请求已经完成的确定，来自线状态阵列的线状态向量可以被写入标签阵列。高速缓存控制器可以跟踪到标签阵列之外的超级线路的待处理线路状态更新，并且线路状态更新可能发生在高速缓存控制器中，而不是等待完成超级线上所有未完成的操作。可以同时维护对多行状态的更新，并计算最新的ECC。

2. 发明申请

US20140281251A1 METHOD AND APPARATUS FOR CACHE LINE STATE UPDATE IN SECTORED CACHE WITH LINE STATE TRACKER 有权
标题翻译：使用线状跟踪器在高速缓存中缓存线状态更新的方法和装置
公开(公告)号：US20140281251A1
公开(公告)日：2014-09-18
申请号：US13827271
申请日：2013-03-14
申请人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
发明人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F12/0826 , G06F12/0864 , G06F12/0895 , G06F2212/60
摘要： Technologies for tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array can be performed. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array.
摘要翻译：描述了用于跟踪对高速缓存超级线路的线路状态的更新的技术。响应于关于超级线的请求，可以执行一个或多个读 - 修改 - 写入（RMW）操作，以（a）线状态阵列的线状态向量和（b）行状态阵列的计数器。基于对超线程的一个或多个请求已经完成的确定，来自线状态阵列的线状态向量可以被写入标签阵列。

3. 发明授权

US07103746B1 Method of sparing memory devices containing pinned memory 有权
标题翻译：节省含有固定存储器的存储器件的方法
公开(公告)号：US07103746B1
公开(公告)日：2006-09-05
申请号：US10749935
申请日：2003-12-31
申请人： Stanley S. Kulick
发明人： Stanley S. Kulick
IPC分类号： G06F12/00 , G06F9/00
CPC分类号： G06F12/0607 , G06F12/126
摘要： Embodiments of the present invention may provide a method of sparing and removing pinned or interleaved memory. When a memory device failure is predicted in a device containing pinned memory, a request may be made for the de-allocation of a freeable memory range 304. When the request for de-allocating the freeable range of memory is accepted 306, the memory data from the failing memory device may be copied to one or more de-allocated memory devices 308. Requests directed to the failing memory device may be re-routed to the replacement memory device(s) 310 and the memory without the deactivated memory device 312 may be re-interleaved.
摘要翻译：本发明的实施例可以提供一种备用和去除固定或交错存储器的方法。当在包含固定存储器的设备中预测存储器件故障时，可以对可释放存储器范围304的去分配进行请求。当接受解除分配可释放存储器范围的请求306时，来自故障存储器件的存储器数据可以被复制到一个或多个解除分配的存储器件308。可以将针对故障存储器设备的请求重新路由到替换存储器设备310，而不需要停用存储器设备312的存储器可能被重新交错。

4. 发明申请

US20130322556A1 ON-PACKAGE INPUT/OUTPUT CLUSTERED INTERFACE HAVING FULL AND HALF-DUPLEX MODES 有权
标题翻译：具有全双工模式的封装输入/输出集群接口
公开(公告)号：US20130322556A1
公开(公告)日：2013-12-05
申请号：US13995015
申请日：2011-12-22
申请人： Thomas P. Thomas , Stanley S. Kulick , Randy B. Osborne
发明人： Thomas P. Thomas , Stanley S. Kulick , Randy B. Osborne
IPC分类号： G06F13/40 , H04B3/02
CPC分类号： G06F13/4068 , G06F13/4086 , G06F15/7825 , H03K19/017545 , H04B3/02 , H04B14/023
摘要： An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.
摘要翻译：一种用于控制片上网络流量的装置和系统。该装置的实施例包括在第一芯片上用于与第二芯片耦合的单端传输电路和单端接收电路，所述传输电路具有阻抗匹配和缺少均衡，接收电路缺少均衡，传输电路和接收电路具有静态可配置特征并且被组织成群集，其中所述簇具有用于不同配置的可配置特征的相同物理层电路设计，所述可配置特征包括半双工模式和全双工模式，其中所述第一芯片和所述第二芯片是在相同的封装上，并且其中用于将第一芯片与第二芯片耦合的多条导线匹配。

5. 发明申请

US20130275664A1 SCALABLE SCHEDULERS FOR MEMORY CONTROLLERS 有权
标题翻译：内存控制器的可扩展调度器
公开(公告)号：US20130275664A1
公开(公告)日：2013-10-17
申请号：US13914993
申请日：2013-06-11
申请人： Philip Abraham , Stanley S. Kulick , Randy B. Osborne
发明人： Philip Abraham , Stanley S. Kulick , Randy B. Osborne
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F9/3834 , G06F9/3842 , G06F9/528 , G06F11/141 , G06F12/0817 , G06F12/0831 , G06F13/1626
摘要： Methods and apparatus to improve throughput and efficiency in memory devices are described. In one embodiment, a memory controller may include scheduler logic to issue read or write requests to a memory device in an optimal fashion, e.g., to maximize bandwidth and/or reduce latency. Other embodiments are also disclosed and claimed.
摘要翻译：描述了用于提高存储器件的产量和效率的方法和装置。在一个实施例中，存储器控制器可以包括调度器逻辑，以最佳方式向存储器件发出读或写请求，例如最大化带宽和/或减少等待时间。还公开并要求保护其他实施例。

6. 发明授权

US08902956B2 On-package input/output clustered interface having full and half-duplex modes 有权
标题翻译：集成式输入/输出集群接口，具有全双工和半双工模式
公开(公告)号：US08902956B2
公开(公告)日：2014-12-02
申请号：US13995015
申请日：2011-12-22
申请人： Thomas P. Thomas , Stanley S. Kulick , Randy B. Osborne
发明人： Thomas P. Thomas , Stanley S. Kulick , Randy B. Osborne
IPC分类号： H04B1/38 , H04B3/02 , G06F15/78 , G06F13/40 , H03K19/0175
CPC分类号： G06F13/4068 , G06F13/4086 , G06F15/7825 , H03K19/017545 , H04B3/02 , H04B14/023
摘要： An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.
摘要翻译：一种用于控制片上网络流量的装置和系统。该装置的实施例包括在第一芯片上用于与第二芯片耦合的单端传输电路和单端接收电路，所述传输电路具有阻抗匹配和缺少均衡，接收电路缺少均衡，传输电路和接收电路具有静态可配置的特征并且被组织成簇，其中所述簇具有用于不同配置的可配置特征的相同的物理层电路设计，所述可配置特征包括半双工模式和全双工模式，其中第一芯片和第二芯片是在相同的封装上，并且其中用于将第一芯片与第二芯片耦合的多条导线匹配。

7. 发明授权

US08327222B2 Mechanism for adjacent-symbol error correction and detection 有权
标题翻译：相邻符号纠错和检测机制
公开(公告)号：US08327222B2
公开(公告)日：2012-12-04
申请号：US12354037
申请日：2009-01-15
申请人： James W. Alexander , Thomas J. Holman , Mark A. Heap , Stanley S. Kulick
发明人： James W. Alexander , Thomas J. Holman , Mark A. Heap , Stanley S. Kulick
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/401 , G11C2029/0409
摘要： According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row.
摘要翻译：根据一个实施例，公开了一种计算机系统。计算机系统包括内存。存储器包括两行或更多行，其中每行具有多个存储器件。计算机系统还包括芯片组。该芯片组包括一个检测/校正电路，用于检测单个和双重符号错误，并纠正每个存储器行的单个符号错误，以及标记以维护每个存储器行内的错误日志。

8. 发明授权

US07509560B2 Mechanism for adjacent-symbol error correction and detection 有权
标题翻译：相邻符号纠错和检测机制
公开(公告)号：US07509560B2
公开(公告)日：2009-03-24
申请号：US10747590
申请日：2003-12-29
申请人： James W. Alexander , Thomas J. Holman , Mark A. Heap , Stanley S. Kulick
发明人： James W. Alexander , Thomas J. Holman , Mark A. Heap , Stanley S. Kulick
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/401 , G11C2029/0409
摘要： According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row.
摘要翻译：根据一个实施例，公开了一种计算机系统。计算机系统包括内存。存储器包括两行或更多行，其中每行具有多个存储器件。计算机系统还包括芯片组。该芯片组包括一个检测/校正电路，用于检测单个和双重符号错误，并纠正每个存储器行的单个符号错误，以及标记以维护每个存储器行内的错误日志。

9. 发明授权

US07386643B2 Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions 有权
标题翻译：保证输入一致输入/输出（I / O）事务的前进进程的机制，用于缓存I / O代理与处理器事务的地址冲突
公开(公告)号：US07386643B2
公开(公告)日：2008-06-10
申请号：US10970015
申请日：2004-10-21
申请人： Sin S. Tan , Stanley S. Kulick , Rajesh S. Pamujula
发明人： Sin S. Tan , Stanley S. Kulick , Rajesh S. Pamujula
IPC分类号： G06F3/00 , G06F9/26 , G06F9/30
CPC分类号： G06F12/0835
摘要： A forwarding device compares a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict exists. The forwarding device completes a first processor-issued transaction of the at least one processor-issued transaction if the address conflict exists and rejects the first coherent I/O transaction. The forwarding device holds remaining processor transactions of the at least one processor-issued transaction that have an address conflict with the first address of the first coherent I/O transaction. The forwarding device transmits the first coherent I/O transaction to an external I/O device, waits for the first coherent I/O transaction to return from the external I/O device, and completes the first coherent I/O transaction. The forwarding device releases the remaining processor transactions once the first coherent I/O transaction has been completed.
摘要翻译：转发设备将来自第一相干输入/输出（I / O）事务的第一地址与来自至少一个处理器发出的事务的地址进行比较，以确定是否存在地址冲突。如果地址冲突存在并且拒绝第一个相干I / O事务，则转发设备完成所述至少一个处理器发布的交易的第一处理器发出的交易。所述转发设备保持所述至少一个处理器发布的交易的剩余处理器事务，其具有与所述第一相干I / O事务的第一地址冲突的地址。转发设备将第一个相干I / O事务发送到外部I / O设备，等待第一个相干I / O事务从外部I / O设备返回，并完成第一个相干I / O事务。一旦完成了第一个相干I / O事务，转发设备将释放剩余的处理器事务。

10. 发明授权

US09143120B2 Mechanisms for clock gating 有权
标题翻译：时钟门控机制
公开(公告)号：US09143120B2
公开(公告)日：2015-09-22
申请号：US13997840
申请日：2011-12-22
申请人： Randy B. Osborne , Stanley S. Kulick , Erin Francom , Thomas P. Thomas
发明人： Randy B. Osborne , Stanley S. Kulick , Erin Francom , Thomas P. Thomas
IPC分类号： G06F1/04 , H03K5/15 , G06F1/06 , G06F1/10 , G06F1/32
CPC分类号： H03K5/15 , G06F1/06 , G06F1/10 , G06F1/32
摘要： Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package. Gating elements within the clock signal distribution network disable the clock signal to one or more portions of the clock signal distribution network. A digital locked loop (DLL) maintains settings without tracking when the clock signal is disabled.
摘要翻译：时钟门控机制时钟发生电路通过集成电路封装内的时钟信号分配网络提供时钟信号。时钟信号分配网络内的选通元件将时钟信号禁止到时钟信号分配网络的一个或多个部分。数字锁定环（DLL）在禁止时钟信号时保持设置而不进行跟踪。

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