专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09336156B2 Method and apparatus for cache line state update in sectored cache with line state tracker 有权
标题翻译：线路状态跟踪器的扇区高速缓存行状态更新方法和装置
公开(公告)号：US09336156B2
公开(公告)日：2016-05-10
申请号：US13827271
申请日：2013-03-14
申请人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
发明人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F12/0826 , G06F12/0864 , G06F12/0895 , G06F2212/60
摘要： A processing device and method for cache control including tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, a cache controller of the processing device can perform one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array. The cache controller can track pending line state updates to a superline outside of the tag array, and a line state update can occur in the cache controller, rather than awaiting completion of all outstanding operations on a superline. Updates to multiple line states can be maintained simultaneously, and up-to-date ECCs computed.
摘要翻译：描述了用于高速缓存控制的处理设备和方法，包括跟踪对高速缓存超线程的线路状态的更新。响应于与超级线相关的请求，处理设备的高速缓存控制器可以执行一个或多个读 - 修改 - 写入（RMW）操作，以（a）线状态阵列的线状态向量和（b）计数器的行状态数组。基于对超线程的一个或多个请求已经完成的确定，来自线状态阵列的线状态向量可以被写入标签阵列。高速缓存控制器可以跟踪到标签阵列之外的超级线路的待处理线路状态更新，并且线路状态更新可能发生在高速缓存控制器中，而不是等待完成超级线上所有未完成的操作。可以同时维护对多行状态的更新，并计算最新的ECC。

2. 发明申请

US20140281251A1 METHOD AND APPARATUS FOR CACHE LINE STATE UPDATE IN SECTORED CACHE WITH LINE STATE TRACKER 有权
标题翻译：使用线状跟踪器在高速缓存中缓存线状态更新的方法和装置
公开(公告)号：US20140281251A1
公开(公告)日：2014-09-18
申请号：US13827271
申请日：2013-03-14
申请人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
发明人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F12/0826 , G06F12/0864 , G06F12/0895 , G06F2212/60
摘要： Technologies for tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array can be performed. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array.
摘要翻译：描述了用于跟踪对高速缓存超级线路的线路状态的更新的技术。响应于关于超级线的请求，可以执行一个或多个读 - 修改 - 写入（RMW）操作，以（a）线状态阵列的线状态向量和（b）行状态阵列的计数器。基于对超线程的一个或多个请求已经完成的确定，来自线状态阵列的线状态向量可以被写入标签阵列。

3. 发明授权

US09298632B2 Hybrid cache state and filter tracking of memory operations during a transaction 有权
标题翻译：混合缓存状态和过滤器跟踪事务期间的内存操作
公开(公告)号：US09298632B2
公开(公告)日：2016-03-29
申请号：US13535788
申请日：2012-06-28
申请人： Robert S. Chappell , Ravi Rajwar , Zhongying Zhang , Jason A. Bessette
发明人： Robert S. Chappell , Ravi Rajwar , Zhongying Zhang , Jason A. Bessette
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08 , G06F9/46
CPC分类号： G06F12/0842 , G06F9/467 , G06F12/0897
摘要： In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，高速缓存存储器可以存储多条高速缓存线，每条高速缓存行包括写入字段以存储写入指示符，以指示在事务性存储器的事务期间是否已经推测写入数据，以及读取集字段以存储多个读取设置指示符，每个指示符指示对应的线程在交易已经提交之前是否已经读取数据。与高速缓冲存储器相关联的压缩过滤器包括第一过滤器存储器，用于在事务已经提交之前存储由第一线程线程读取的高速缓存线的高速缓存行地址的表示。描述和要求保护其他实施例。

4. 发明授权

US06370625B1 Method and apparatus for lock synchronization in a microprocessor system 有权
标题翻译：用于微处理器系统中锁同步的方法和装置
公开(公告)号：US06370625B1
公开(公告)日：2002-04-09
申请号：US09474698
申请日：1999-12-29
申请人： Douglas M. Carmean , Harish Kumar , Brent E. Lince , Michael D. Upton , Zhongying Zhang
发明人： Douglas M. Carmean , Harish Kumar , Brent E. Lince , Michael D. Upton , Zhongying Zhang
IPC分类号： G06F1318
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/3842
摘要： A method of controlling operations by one or more processors includes granting ownership of a memory location having data stored therein to a first processor and performing, in an atomic manner by the first processor, a read operation to load the data from the memory location to a register, a modify operation to modify the data in the register, and a write operation to store the data from the register to the memory location. The method also prevents other operations directed towards the data by a second processor while the read, modify, and write operations are performed by the first processor, and vice versa. Ownership of the memory location is released after performing the read, modify, and write operations so as to allow the first or second processors to perform subsequent atomic operations.
摘要翻译：一种控制一个或多个处理器的操作的方法包括将具有其中存储的数据的存储器位置的所有权授予第一处理器，并以原子方式由第一处理器执行读取操作，以将数据从存储器位置加载到注册，修改操作以修改寄存器中的数据，以及写入操作，以将数据从寄存器存储到存储器位置。当读取，修改和写入操作由第一处理器执行时，该方法还防止由第二处理器指向数据的其他操作，反之亦然。在执行读取，修改和写入操作之后释放内存位置的所有权，以便允许第一或第二处理器执行后续的原子操作。

5. 发明申请

US20050216673A1 Method and apparatus handling locks 审中-公开
标题翻译：方法和设备处理锁
公开(公告)号：US20050216673A1
公开(公告)日：2005-09-29
申请号：US11131765
申请日：2005-05-17
申请人： Harish Kumar , Aravindh Baktha , Mike Upton , KS Venkatraman , Herbert Hum , Zhongying Zhang
发明人： Harish Kumar , Aravindh Baktha , Mike Upton , KS Venkatraman , Herbert Hum , Zhongying Zhang
IPC分类号： G06F9/312 , G06F9/318 , G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3836 , G06F9/3004 , G06F9/30087 , G06F9/30181 , G06F9/30185 , G06F9/3834 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F12/0815
摘要： A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a processing device.
摘要翻译：一种用于确定与锁定的加载指令相关联的属性并基于所述锁定加载指令的属性来选择锁定协议的方法和装置。还公开了一种用于并行执行与处理装置的多个线程相关联的各个锁定序列的方法。

6. 发明授权

US06922745B2 Method and apparatus for handling locks 有权
标题翻译：处理锁的方法和装置
公开(公告)号：US06922745B2
公开(公告)日：2005-07-26
申请号：US10139215
申请日：2002-05-02
申请人： Harish Kumar , Aravindh Baktha , Mike D. Upton , KS Venkatraman , Herbert H. Hum , Zhongying Zhang
发明人： Harish Kumar , Aravindh Baktha , Mike D. Upton , KS Venkatraman , Herbert H. Hum , Zhongying Zhang
IPC分类号： G06F9/312 , G06F9/318 , G06F9/38 , G06F12/08 , G06F12/14
CPC分类号： G06F9/3836 , G06F9/3004 , G06F9/30087 , G06F9/30181 , G06F9/30185 , G06F9/3834 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F12/0815
摘要： A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a processing device.
摘要翻译：一种用于确定与锁定的加载指令相关联的属性并基于所述锁定加载指令的属性来选择锁定协议的方法和装置。还公开了一种用于并行执行与处理装置的多个线程相关联的各个锁定序列的方法。

7. 发明申请

US20200310798A1 Technology For Providing Memory Atomicity With Low Overhead 审中-公开
公开(公告)号：US20200310798A1
公开(公告)日：2020-10-01
申请号：US16367409
申请日：2019-03-28
申请人： Manjunath Shevgoor , Mark Joseph Dechene , Vineeth Mekkat , Jason Michael Agron , Zhongying Zhang
发明人： Manjunath Shevgoor , Mark Joseph Dechene , Vineeth Mekkat , Jason Michael Agron , Zhongying Zhang
IPC分类号： G06F9/30 , G06F9/38
摘要： An integrated circuit with support for memory atomicity comprises a processor core. The processor core comprises a data cache unit (DCU), a store buffer (SB), a retirement unit, and memory atomicity facilities. The memory atomicity facilities are configured, when engaged, to (a) add an SB entry to the SB, in response to the processor core executing a store instruction that is part of an atomic region of code; (b) cause the SB entry to become senior, in response to the retirement unit retiring the store instruction; and (c) cause the SB entry to become walk enabled, in response to the retirement unit committing a transaction associated with the atomic region. Other embodiments are described and claimed.

8. 发明申请

US20190303150A1 APPARATUS AND METHOD FOR AN EARLY PAGE PREDICTOR FOR A MEMORY PAGING SUBSYSTEM 审中-公开
公开(公告)号：US20190303150A1
公开(公告)日：2019-10-03
申请号：US15941976
申请日：2018-03-30
申请人： Mark Dechene , Manjunath Shevgoor , Faruk Guvenilir , Zhongying Zhang , Jonathan Perry
发明人： Mark Dechene , Manjunath Shevgoor , Faruk Guvenilir , Zhongying Zhang , Jonathan Perry
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F12/1027
摘要： An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.

9. 发明申请

US20080059753A1 Scheduling operations corresponding to store instructions 审中-公开
标题翻译：与存储指令对应的调度操作
公开(公告)号：US20080059753A1
公开(公告)日：2008-03-06
申请号：US11512819
申请日：2006-08-30
申请人： Sebastien Hily , Zhongying Zhang , Ranjani Iyer , Stephan Jourdan , Per Hammarlund
发明人： Sebastien Hily , Zhongying Zhang , Ranjani Iyer , Stephan Jourdan , Per Hammarlund
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/3857
摘要： Methods and apparatus to redispatch an operation for execution in a processor are described. In one embodiment, a virtual address corresponding to a store instruction may be reselected for translation into a physical address in response to remaining unselected during a previous selection process. Other embodiments are also described.
摘要翻译：描述用于重新分配在处理器中执行的操作的方法和装置。在一个实施例中，对应于存储指令的虚拟地址可以被重新选择用于响应于在先前的选择过程期间未被选择而被翻译成物理地址。还描述了其它实施例。

10. 发明申请

US20140006698A1 Hybrid Cache State And Filter Tracking Of Memory Operations During A Transaction 有权
标题翻译：混合缓存状态和过滤器跟踪事务期间的内存操作
公开(公告)号：US20140006698A1
公开(公告)日：2014-01-02
申请号：US13535788
申请日：2012-06-28
申请人： Robert S. Chappell , Ravi Rajwar , Zhongying Zhang , Jason A. Bessette
发明人： Robert S. Chappell , Ravi Rajwar , Zhongying Zhang , Jason A. Bessette
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0842 , G06F9/467 , G06F12/0897
摘要： In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，高速缓存存储器可以存储多条高速缓存线，每条高速缓存行包括写入字段以存储写入指示符，以指示在事务性存储器的事务期间是否已经推测写入数据，以及读取集字段以存储多个读取设置指示符，每个指示符指示对应的线程在交易已经提交之前是否已经读取数据。与高速缓冲存储器相关联的压缩过滤器包括第一过滤器存储器，用于在事务已经提交之前存储由第一线程线程读取的高速缓存线的高速缓存行地址的表示。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式