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1. 发明申请

US20130122671A1 PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS 有权
标题翻译：去除NiPtSi应用的Ni和Pt残留物的工艺
公开(公告)号：US20130122671A1
公开(公告)日：2013-05-16
申请号：US13296444
申请日：2011-11-15
申请人： Anh Duong , Sean Barstow , Clemens Fitz , John Foster , Olov Karlsson , Bei Li , James Mavrinac
发明人： Anh Duong , Sean Barstow , Clemens Fitz , John Foster , Olov Karlsson , Bei Li , James Mavrinac
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/02068 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.
摘要翻译：本发明公开了一种在镍铂硅化过程中清除半导体衬底的残留物的方法。本发明的实施方案提供了一种多步骤清洗方法，包括在第一次退火之后将基底暴露于硝酸溶液，然后在第二次退火之后暴露于王水溶液中。可以将底物任选地暴露于盐酸溶液中以完全除去任何剩余的铂残余物。

2. 发明授权

US08513117B2 Process to remove Ni and Pt residues for NiPtSi applications 有权
标题翻译：去除NiPtSi应用的Ni和Pt残留物的工艺
公开(公告)号：US08513117B2
公开(公告)日：2013-08-20
申请号：US13296444
申请日：2011-11-15
申请人： Anh Duong , Sean Barstow , Clemens Fitz , John Foster , Olov Karlsson , Bei Li , James Mavrinac
发明人： Anh Duong , Sean Barstow , Clemens Fitz , John Foster , Olov Karlsson , Bei Li , James Mavrinac
IPC分类号： H01L21/44
CPC分类号： H01L21/02068 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.
摘要翻译：本发明公开了一种在镍铂硅化过程中清除半导体衬底的残留物的方法。本发明的实施方案提供了一种多步骤清洗方法，包括在第一次退火之后将基底暴露于硝酸溶液，然后在第二次退火之后暴露于王水溶液中。可以将底物任选地暴露于盐酸溶液中以完全除去任何剩余的铂残余物。

3. 发明授权

US08466058B2 Process to remove Ni and Pt residues for NiPtSi applications using chlorine gas 有权
标题翻译：使用氯气去除NiPtSi应用的Ni和Pt残留物的工艺
公开(公告)号：US08466058B2
公开(公告)日：2013-06-18
申请号：US13295333
申请日：2011-11-14
申请人： Anh Duong , John Foster , Olov Karlsson , James Mavrinac , Usha Raghuram
发明人： Anh Duong , John Foster , Olov Karlsson , James Mavrinac , Usha Raghuram
IPC分类号： H01L21/44
CPC分类号： H01L21/324 , H01L21/02068 , H01L21/28 , H01L21/28052 , H01L21/28518 , H01L21/67028 , H01L21/67057 , H01L29/665
摘要： The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.
摘要翻译：本发明公开了一种在镍铂硅化过程中清除半导体衬底的残留物的方法。镍和铂的后硅化残留物只能通过王水溶液（包括硝酸和盐酸的混合物）而被充分除去。因此，本发明的实施方案提供多步残留物清洗，包括将底物暴露于王水溶液，随后暴露于氯气或包含溶解的氯气的溶液中，其可进一步与剩余的铂残基反应，使得它更可溶于水溶液，从而从基底表面溶解。

4. 发明申请

US20130122670A1 PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS USING CHLORINE GAS 有权
标题翻译：使用氯仿气体去除NiPtSi应用的Ni和Pt残留物的工艺
公开(公告)号：US20130122670A1
公开(公告)日：2013-05-16
申请号：US13295333
申请日：2011-11-14
申请人： Anh Duong , John Foster , Olov Karlsson , James Mavrinac , Usha Raghuram
发明人： Anh Duong , John Foster , Olov Karlsson , James Mavrinac , Usha Raghuram
IPC分类号： H01L21/336 , B08B3/08 , H01L21/28
CPC分类号： H01L21/324 , H01L21/02068 , H01L21/28 , H01L21/28052 , H01L21/28518 , H01L21/67028 , H01L21/67057 , H01L29/665
摘要： The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.
摘要翻译：本发明公开了一种在镍铂硅化过程中清除半导体衬底的残留物的方法。镍和铂的后硅化残留物只能通过王水溶液（包括硝酸和盐酸的混合物）而被充分除去。因此，本发明的实施方案提供多步残留物清洗，包括将底物暴露于王水溶液，随后暴露于氯气或包含溶解的氯气的溶液中，其可进一步与剩余的铂残基反应，使得它更可溶于水溶液，从而从基底表面溶解。

5. 发明授权

US08854067B2 Circular transmission line methods compatible with combinatorial processing of semiconductors 有权
标题翻译：圆形传输线方法兼容半导体的组合处理
公开(公告)号：US08854067B2
公开(公告)日：2014-10-07
申请号：US13594292
申请日：2012-08-24
申请人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
发明人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
IPC分类号： G01R27/08 , G01R31/28
CPC分类号： G01R27/08 , G01R31/2831 , H01L22/14 , H01L22/20
摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要翻译：描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

6. 发明申请

US20130316472A1 HIGH PRODUCTIVITY COMBINATORIAL OXIDE TERRACING AND PVD/ALD METAL DEPOSITION COMBINED WITH LITHOGRAPHY FOR GATE WORK FUNCTION EXTRACTION 有权
标题翻译：高生产率组合氧化物触媒和PVD / ALD金属沉积与门式工作功能提取相结合
公开(公告)号：US20130316472A1
公开(公告)日：2013-11-28
申请号：US13480023
申请日：2012-05-24
申请人： Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
发明人： Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
IPC分类号： H01L21/66
CPC分类号： H01L29/66181 , G01N27/002 , H01L22/14 , H01L22/20
摘要： Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
摘要翻译：使用光刻图案化的金属栅极高k电容器结构使用组合工作流程提取门功函数。氧化物梯田，以及用于金属沉积的高生产率组合工艺流程可为高性能逻辑晶体管提供最佳的高k栅介质和金属栅极解决方案。高生产率组合技术可以为PMOS和NMOS晶体管的给定高k介质金属栅极叠层提供有效的工作函数的评估，这对于识别和选择正确的材料至关重要。

7. 发明授权

US08735302B2 High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction 有权
标题翻译：高生产率组合氧化物梯度和PVD / ALD金属沉积结合光刻用于栅极功能提取
公开(公告)号：US08735302B2
公开(公告)日：2014-05-27
申请号：US13480023
申请日：2012-05-24
申请人： Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
发明人： Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/66181 , G01N27/002 , H01L22/14 , H01L22/20
摘要： Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
摘要翻译：使用光刻图案化的金属栅极高k电容器结构使用组合工作流程提取门功函数。氧化物梯田，以及用于金属沉积的高生产率组合工艺流程可为高性能逻辑晶体管提供最佳的高k栅介质和金属栅极解决方案。高生产率组合技术可以为PMOS和NMOS晶体管的给定高k介质金属栅极叠层提供有效的工作函数的评估，这对于识别和选择正确的材料至关重要。

8. 发明申请

US20140055152A1 CIRCULAR TRANSMISSION LINE METHODS COMPATIBLE WITH COMBINATORIAL PROCESSING OF SEMICONDUCTORS 有权
标题翻译：圆形传输线方法与半导体的组合处理兼容
公开(公告)号：US20140055152A1
公开(公告)日：2014-02-27
申请号：US13594292
申请日：2012-08-24
申请人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
发明人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
IPC分类号： G01R27/08
CPC分类号： G01R27/08 , G01R31/2831 , H01L22/14 , H01L22/20
摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要翻译：描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

9. 发明申请

US20160255824A1 Insect Trapping Device 审中-公开
标题翻译：昆虫捕获装置
公开(公告)号：US20160255824A1
公开(公告)日：2016-09-08
申请号：US14640064
申请日：2015-03-06
申请人： John Foster
发明人： John Foster
IPC分类号： A01M3/00 , A01M3/02
CPC分类号： A01M3/005 , A01M3/025
摘要： An insect trapping device traps, kills and facilitates disposal of an insect. The device includes a handle which is hollow defining a conduit extending between a first end and a second end. A fan coupled to the handle in the conduit such that the fan provides suction into the first end of the handle. A cup is coupled to the first end of the handle for directing an insect into the first end of the handle. A receptacle is coupled to the second end of the handle and vented end such that the fan urges air flow out through the receptacle wherein the receptacle receives and holds the insect sucked through the first end of the handle.
摘要翻译：昆虫捕获装置捕获，杀死并促进昆虫的处置。该装置包括一个手柄，该手柄是中空的，限定了在第一端和第二端之间延伸的导管。风扇，其联接到管道中的把手，使得风扇向手柄的第一端提供抽吸。杯子联接到手柄的第一端，以将昆虫引导到手柄的第一端。容器连接到手柄的第二端和通风端，使得风扇促使空气通过容器流出，其中容器容纳并保持通过手柄的第一端吸入的昆虫。

10. 发明申请

US20140011367A1 Low Temperature Etching of Silicon Nitride Structures Using Phosphoric Acid Solutions 失效
标题翻译：使用磷酸溶液的氮化硅结构的低温蚀刻
公开(公告)号：US20140011367A1
公开(公告)日：2014-01-09
申请号：US13541397
申请日：2012-07-03
申请人： Gregory Nowling , John Foster
发明人： Gregory Nowling , John Foster
IPC分类号： H01L21/306
CPC分类号： H01L21/31111 , H01L21/67086 , H01L29/6653
摘要： Provided are methods for processing semiconductor substrates. The methods involve etching silicon nitride structures using phosphoric acid solutions maintained at low temperatures, such as between about 110° C. and 130° C. These temperatures provide adequate etching rates and do not damage surrounding metal silicide and silicon oxide structures. The etching rates of silicon nitride may be 10 Angstroms per minute and greater. Lower temperatures also allow decreasing concentrations of phosphoric acid in the etching solutions, which in some embodiments may be less than 90 weight percent. As a result, more selective etching of the silicon nitride structures may be achieved. This selectivity may be as high as hundred times relative to the silicide and silicon oxide structures. The surface conductivity of the silicide structures may remain substantially unchanged by this etching process.
摘要翻译：提供了用于处理半导体衬底的方法。该方法包括使用保持在低温（例如约110℃至130℃）之间的磷酸溶液来蚀刻氮化硅结构。这些温度提供足够的蚀刻速率，并且不会损坏周围的金属硅化物和氧化硅结构。氮化硅的蚀刻速率可以为每分钟10埃或更高。较低的温度也允许蚀刻溶液中磷酸的浓度降低，在一些实施方案中磷酸的浓度可以小于90重量％。结果，可以实现对氮化硅结构的更多的选择性蚀刻。相对于硅化物和氧化硅结构，该选择性可高达百倍。通过该蚀刻工艺，硅化物结构的表面电导率可以保持基本不变。

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