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1. 发明授权

US06169004A Production method for a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06169004A
公开(公告)日：2001-01-02
申请号：US09093787
申请日：1998-06-09
申请人： Bunji Mizuno , Kenji Okada , Ichirou Nakayama
发明人： Bunji Mizuno , Kenji Okada , Ichirou Nakayama
IPC分类号： H01L21336
CPC分类号： H01L21/02238 , C23C16/48 , C23C16/482 , C23C16/484 , C23C16/485 , C23C16/486 , C23C16/487 , H01L21/02167 , H01L21/0217 , H01L21/02211 , H01L21/02227 , H01L21/02247 , H01L21/02252 , H01L21/02277 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28512 , H01L21/28525 , H01L21/28556 , H01L21/31608
摘要： A P-type impurity layer, a silicon monocrystal film, a silicon oxide film and a crystal silicon film are successively formed on a semiconductor substrate by introducing appropriate functional gases on the semiconductor substrate, while irradiating the semiconductor substrate with ionizing radiation or light at a temperature lower than 250° C. After forming a photoresist on the crystal silicon film at a temperature lower than 250° C., the resultant semiconductor substrate is subjected to etching by using the photoresist as a mask, so as to form a gate electrode B out of the silicon oxide film and a gate insulating film out of the silicon oxide film. Then, the resultant semiconductor substrate is subjected to etching again by using the gate electrode as a mask, so as to form a channel region out of the P-type impurity layer. A source electrode and a drain electrode are formed on the respective sides of the gate electrode on the semiconductor substrate by introducing an appropriate functional. gas, while irradiating the semiconductor substrate with ionizing radiation or light at a temperature lower than 250° C.
摘要翻译：在半导体衬底上依次形成P型杂质层，硅单晶膜，氧化硅膜和晶体硅膜，通过在半导体衬底上引入适当的功能气体，同时用电离辐射或光照射半导体衬底温度低于250℃。在低于250℃的温度下在晶体硅膜上形成光致抗蚀剂后，通过使用光致抗蚀剂作为掩模对所得到的半导体衬底进行蚀刻，以形成栅电极B 并且从氧化硅膜出来的栅极绝缘膜。然后，通过使用栅电极作为掩模，再次对所得到的半导体衬底进行蚀刻，从而在P型杂质层之外形成沟道区。通过引入适当的功能，在半导体衬底上的栅电极的各个侧面上形成源电极和漏电极。气体，同时用电离辐射或低于250℃的光照射半导体衬底。

2. 发明授权

US5817559A Production method for a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5817559A
公开(公告)日：1998-10-06
申请号：US440979
申请日：1995-05-15
申请人： Bunji Mizuno , Kenji Okada , Ichirou Nakayama
发明人： Bunji Mizuno , Kenji Okada , Ichirou Nakayama
IPC分类号： C23C16/48 , H01L21/205 , H01L21/285 , H01L21/316 , H01L21/336
CPC分类号： H01L21/02238 , C23C16/48 , C23C16/482 , C23C16/484 , C23C16/485 , C23C16/486 , C23C16/487 , H01L21/02167 , H01L21/0217 , H01L21/02211 , H01L21/02227 , H01L21/02247 , H01L21/02252 , H01L21/02277 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28512 , H01L21/28525 , H01L21/28556 , H01L21/31608
摘要： A P-type impurity layer, a silicon monocrystal film, a silicon oxide film and a crystal silicon film are successively formed on a semiconductor substrate by introducing appropriate functional gases on the semiconductor substrate, while irradiating the semiconductor substrate with ionizing radiation or light at a temperature lower than 250.degree. C. After forming a photoresist on the crystal silicon film at a temperature lower than 250.degree. C., the resultant semiconductor substrate is subjected to etching by using the photoresist as a mask, so as to form a gate electrode B out of the silicon oxide film and a gate insulating film out of the silicon oxide film. Then, the resultant semiconductor substrate is subjected to etching again by using the gate electrode as a mask, so as to form a channel region out of the P-type impurity layer. A source electrode and a drain electrode are formed on the respective sides of the gate electrode on the semiconductor substrate by introducing an appropriate functional gas, while irradiating the semiconductor substrate with ionizing radiation or light at a temperature lower than 250.degree. C.
摘要翻译：在半导体衬底上依次形成P型杂质层，硅单晶膜，氧化硅膜和晶体硅膜，通过在半导体衬底上引入适当的功能气体，同时用电离辐射或光照射半导体衬底温度低于250℃。在低于250℃的温度下在晶体硅膜上形成光致抗蚀剂后，通过使用光致抗蚀剂作为掩模对所得半导体衬底进行蚀刻，以形成栅电极B 并且从氧化硅膜出来的栅极绝缘膜。然后，通过使用栅电极作为掩模，再次对所得到的半导体衬底进行蚀刻，从而在P型杂质层之外形成沟道区。通过引入适当的功能气体，在电离辐射或半导体衬底的温度低于250℃的光照射半导体衬底的同时，在半导体衬底上的栅极的各个侧面上形成源电极和漏电极。

3. 发明授权

US08536000B2 Method for producing a semiconductor device have fin-shaped semiconductor regions 有权
标题翻译：制造半导体器件的方法具有鳍状半导体区域
公开(公告)号：US08536000B2
公开(公告)日：2013-09-17
申请号：US13185221
申请日：2011-07-18
申请人： Yuichiro Sasaki , Keiichi Nakamoto , Katsumi Okashita , Hisataka Kanada , Bunji Mizuno
发明人： Yuichiro Sasaki , Keiichi Nakamoto , Katsumi Okashita , Hisataka Kanada , Bunji Mizuno
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/66803 , H01L29/66795 , H01L29/7854
摘要： First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2′ of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.
摘要翻译：第一和第二栅极绝缘膜形成为至少覆盖第一和第二鳍状半导体区域的上角。位于第一栅极绝缘膜外侧的第一鳍状半导体区域的上角的曲率半径r1'大于位于第一栅极下方的第一鳍状半导体区域的上角的曲率半径r1 绝缘膜，小于或等于2×r1。位于第二栅极绝缘膜外侧的第二鳍状半导体区域的上角的曲率半径r2'大于位于第二栅极下方的第二鳍状半导体区域的上角的曲率半径r2 绝缘膜，小于或等于2×r2。

4. 发明授权

US08258585B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08258585B2
公开(公告)日：2012-09-04
申请号：US12676102
申请日：2009-04-30
申请人： Yuichiro Sasaki , Katsumi Okashita , Keiichi Nakamoto , Bunji Mizuno
发明人： Yuichiro Sasaki , Katsumi Okashita , Keiichi Nakamoto , Bunji Mizuno
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/66803
摘要： A semiconductor device includes: a fin-type semiconductor region (13) formed on a substrate (11); a gate insulating film (14) formed so as to cover an upper surface and both side surfaces of a predetermined portion of the fin-type semiconductor region (13); a gate electrode (15) formed on the gate insulating film (14); and an impurity region (17) formed on both sides of the gate electrode (15) in the fin-type semiconductor region (13). An impurity blocking portion (15a) for blocking the introduction of impurities is provided adjacent both sides of the gate electrode (15) over an upper surface of the fin-type semiconductor region (13).
摘要翻译：半导体器件包括：形成在衬底（11）上的鳍状半导体区域（13）; 形成为覆盖所述鳍状半导体区域（13）的预定部分的上表面和两个侧面的栅极绝缘膜（14）; 形成在栅极绝缘膜（14）上的栅电极（15）; 以及形成在鳍式半导体区域（13）中的栅电极（15）的两侧的杂质区域（17）。在鳍型半导体区域（13）的上表面上，在栅电极（15）的两侧附近设置用于阻止引入杂质的杂质阻挡部（15a）。

5. 发明申请

US20120186519A1 PLASMA DOPING METHOD AND APPARATUS 审中-公开
标题翻译：等离子喷涂方法和装置
公开(公告)号：US20120186519A1
公开(公告)日：2012-07-26
申请号：US13358277
申请日：2012-01-25
申请人： Tomohiro Okumura , Yuichiro Sasaki , Katsumi Okashita , Hiroyuki Ito , Bunji Mizuno , Cheng-Guo Jin , Ichiro Nakayama
发明人： Tomohiro Okumura , Yuichiro Sasaki , Katsumi Okashita , Hiroyuki Ito , Bunji Mizuno , Cheng-Guo Jin , Ichiro Nakayama
IPC分类号： C23C16/50
CPC分类号： H01L21/2236 , H01J37/321 , H01J37/32412 , H01J2237/2001
摘要： A plasma doping method and apparatus in which a prescribed gas is introduced into a vacuum container while being exhausted by a turbomolecular pump as an exhaust apparatus. The pressure in the vacuum container is kept at a prescribed value by a pressure regulating valve. High-frequency electric power of 13.56 MHz is supplied to a coil disposed close to a dielectric window which is opposed to a sample electrode, whereby induction-coupled plasma is generated in the vacuum container. Every time a prescribed number of samples have been processed, a dummy sample is subjected to plasma doping and then to heating. The conditions for processing of a sample are controlled so that the measurement value of the surface sheet resistance becomes equal to a prescribed value, whereby the controllability of the impurity concentration can be increased.
摘要翻译：一种等离子体掺杂方法和装置，其中将预定气体通过作为排气装置的涡轮分子泵排出而被引入真空容器中。通过压力调节阀将真空容器内的压力保持在规定值。将13.56MHz的高频电力供给到与样品电极相对的电介质窗附近设置的线圈，由此在真空容器内产生感应耦合等离子体。每当处理规定数量的样品时，将虚拟样品进行等离子体掺杂，然后进行加热。控制处理样品的条件使得表面薄层电阻的测量值等于规定值，从而可以提高杂质浓度的可控性。

6. 发明授权

US08124507B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08124507B2
公开(公告)日：2012-02-28
申请号：US12937169
申请日：2010-03-04
申请人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
发明人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
IPC分类号： H01L29/78 , H01L21/223
CPC分类号： H01L29/785 , H01L29/66795
摘要： A fin-type semiconductor region (103) is formed on a substrate (101), and then a resist pattern (105) is formed on the substrate (101). An impurity is implanted into the fin-type semiconductor region (103) by a plasma doping process using the resist pattern (105) as a mask, and then at least a side of the fin-type semiconductor region (103) is covered with a protective film (107). Thereafter, the resist pattern (105) is removed by cleaning using a chemical solution, and then the impurity implanted into the fin-type semiconductor region (103) is activated by heat treatment.
摘要翻译：在基板（101）上形成翅片型半导体区域（103），然后在基板（101）上形成抗蚀图案（105）。通过使用抗蚀剂图案（105）作为掩模的等离子体掺杂工艺将杂质注入到鳍式半导体区域（103）中，然后用鳍状半导体区域（103）的至少一侧覆盖保护膜（107）。此后，通过使用化学溶液的清洗除去抗蚀剂图案（105），然后通过热处理激活注入到鳍式半导体区域（103）中的杂质。

7. 发明授权

US08105926B2 Method for producing a semiconductor device by plasma doping a semiconductor region to form an impurity region 有权
标题翻译：通过等离子体掺杂半导体区域以形成杂质区域来制造半导体器件的方法
公开(公告)号：US08105926B2
公开(公告)日：2012-01-31
申请号：US12853840
申请日：2010-08-10
申请人： Yuichiro Sasaki , Katsumi Okashita , Keiichi Nakamoto , Hiroyuki Ito , Bunji Mizuno
发明人： Yuichiro Sasaki , Katsumi Okashita , Keiichi Nakamoto , Hiroyuki Ito , Bunji Mizuno
IPC分类号： H01L21/425
CPC分类号： H01L29/785 , H01L29/66803 , H01L29/78621
摘要： A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.
摘要翻译：在基板上形成具有上表面和侧面的半导体区域。第一杂质区形成在半导体区域的上部。第二杂质区域形成在半导体区域的侧部。第二杂质区的电阻率基本上等于或小于第一杂质区的电阻率。

8. 发明申请

US20110147813A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110147813A1
公开(公告)日：2011-06-23
申请号：US12944224
申请日：2010-11-11
申请人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
发明人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
IPC分类号： H01L29/772 , H01L21/22
CPC分类号： H01L29/785 , H01L21/2236 , H01L29/66795
摘要： A method for fabricating a semiconductor device includes: forming a fin-type semiconductor region on a substrate; and introducing an n-type impurity into at least a side of the fin-type semiconductor region by a plasma doping process, thereby forming an n-type impurity region in the side of the fin-type semiconductor region. In the introducing the n-type impurity, when a source power in the plasma doping process is denoted by a character Y [W], the supply of a gas containing the n-type impurity per unit time and per unit volume is set greater than or equal to 5.1×10−8/(1.72.51/24.51)×(Y/500)) [mol/(min·L·sec)], and the supply of a diluent gas per unit time and per unit volume is set greater than or equal to 1.7×10−4(202.51/24.51)×(Y/500)) [mol/(min·L·sec)].
摘要翻译：一种制造半导体器件的方法包括：在衬底上形成翅片型半导体区域; 并且通过等离子体掺杂工艺将n型杂质引入到鳍式半导体区域的至少一侧，从而在鳍式半导体区域的侧面形成n型杂质区域。在引入n型杂质时，当等离子体掺杂过程中的源功率由字符Y [W]表示时，每单位时间和每单位体积的含有n型杂质的气体的供给被设定为大于或等于5.1×10-8 /（1.72.51 / 24.51）×（Y / 500））[mol /（min·L·sec）]，每单位时间和每单位体积的稀释气体供应量大于或等于1.7×10-4（202.51 / 24.51）×（Y / 500））[mol /（min·L·sec）]]。

9. 发明授权

US07754503B2 Method for producing semiconductor device and semiconductor producing apparatus 有权
标题翻译：半导体装置及半导体制造装置的制造方法
公开(公告)号：US07754503B2
公开(公告)日：2010-07-13
申请号：US12158906
申请日：2008-01-09
申请人： Yuichiro Sasaki , Katsumi Okashita , Keiichi Nakamoto , Hiroyuki Ito , Bunji Mizuno
发明人： Yuichiro Sasaki , Katsumi Okashita , Keiichi Nakamoto , Hiroyuki Ito , Bunji Mizuno
IPC分类号： H01L21/20
CPC分类号： H01L21/2236 , H01L29/6659 , H01L29/7833
摘要： A plasma of a gas containing an impurity is produced through a discharge in a vacuum chamber, and a plurality of substrates are successively doped with the impurity by using the plasma, wherein a plasma doping condition of a subject substrate is adjusted based on an accumulated discharge time until the subject substrate is placed in the vacuum chamber.
摘要翻译：通过在真空室中的放电产生含有杂质的气体的等离子体，并且通过使用等离子体使多个基板依次掺杂有杂质，其中基于累积放电来调整被检体基板的等离子体掺杂状态直到目标基板被放置在真空室中。

10. 发明申请

US20100148323A1 IMPURITY INTRODUCING METHOD USING OPTICAL CHARACTERISTICS TO DETERMINE ANNEALING CONDITIONS 有权
标题翻译：使用光学特性确定退火条件的引进方法
公开(公告)号：US20100148323A1
公开(公告)日：2010-06-17
申请号：US12710482
申请日：2010-02-23
申请人： Cheng-Guo Jin , Yuichiro Sasaki , Bunji Mizuno
发明人： Cheng-Guo Jin , Yuichiro Sasaki , Bunji Mizuno
IPC分类号： H01L29/06 , H01L21/38
CPC分类号： H01L21/2236 , H01L21/26513 , H01L21/268 , H01L22/12 , H01L22/20 , H01L22/26
摘要： A subject of the present invention is to realize an impurity doping not to bring about a rise of a substrate temperature. Another subject of the present invention is to measure optically physical properties of a lattice defect generated by the impurity doping step to control such that subsequent steps are optimized. An impurity doping method, includes a step of doping an impurity into a surface of a solid state base body, a step of measuring an optical characteristic of an area into which the impurity is doped, a step of selecting annealing conditions based on a measurement result to meet the optical characteristic of the area into which the impurity is doped, and a step of annealing the area into which the impurity is doped, based on the selected annealing conditions.
摘要翻译：本发明的目的是实现杂质掺杂不会引起衬底温度的升高。本发明的另一主题是测量由杂质掺杂步骤产生的晶格缺陷的光学物理性能，以便控制以使后续步骤被优化。杂质掺杂方法包括将杂质掺杂到固态基体的表面的步骤，测量掺杂杂质的区域的光学特性的步骤，基于测量结果选择退火条件的步骤以满足掺杂杂质的区域的光学特性，以及基于所选择的退火条件对杂质掺杂的区域进行退火的步骤。

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