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1. 发明授权

US07678637B2 CMOS fabrication process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US07678637B2
公开(公告)日：2010-03-16
申请号：US12209270
申请日：2008-09-12
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

2. 发明申请

US20100133624A1 CMOS Fabrication Process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US20100133624A1
公开(公告)日：2010-06-03
申请号：US12696215
申请日：2010-01-29
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

3. 发明授权

US08125035B2 CMOS fabrication process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US08125035B2
公开(公告)日：2012-02-28
申请号：US12696215
申请日：2010-01-29
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

4. 发明申请

US20090079008A1 CMOS Fabrication Process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US20090079008A1
公开(公告)日：2009-03-26
申请号：US12209270
申请日：2008-09-12
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

5. 发明授权

US07211481B2 Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer 有权
标题翻译：使用封端的多晶硅层减少PMOS器件的掺杂剂扩散的方法来应变NMOS器件
公开(公告)号：US07211481B2
公开(公告)日：2007-05-01
申请号：US11060841
申请日：2005-02-18
申请人： Manoj Mehrotra , Lahir Shaik Adam , Song Zhao , Mahalingam Nandakumar
发明人： Manoj Mehrotra , Lahir Shaik Adam , Song Zhao , Mahalingam Nandakumar
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/6659 , H01L29/7843 , Y10S438/902
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.
摘要翻译：本发明通过提供制造方法来促进半导体制造，所述方法对设备的沟道区域施加拉伸应变，同时减轻不期望的掺杂剂扩散，这降低了器件性能。源极/漏极区形成在PMOS区（102）的有源区中。执行第一热处理，其激活所形成的源极/漏极区域和在注入的掺杂剂（104）中的驱动。随后，在NMOS区域（106）的有源区域中形成源极/漏极区域。然后，在器件（108）上方形成封盖的多晶硅层。执行第二热处理（110），其使得封端的多晶硅层引入器件的沟道区域的应变。由于第一热处理，减少了在第二热处理期间不期望的掺杂剂扩散，特别是不期望的p型掺杂剂扩散。

6. 发明授权

US08101476B2 Stress memorization dielectric optimized for NMOS and PMOS 有权
标题翻译：针对NMOS和PMOS优化的应力记忆电介质
公开(公告)号：US08101476B2
公开(公告)日：2012-01-24
申请号：US12541335
申请日：2009-08-14
申请人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
发明人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/3185 , H01L21/823807 , H01L29/7843 , H01L29/7845
摘要： A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not through NMOS source and drain anneal. A SiN dielectric layer is deposited such that an area ratio of a Si—H peak to a N—H peak in a FTIR spectrum is greater than 7 and a tensile stress of the SiN dielectric is greater than 150 MPa. The CMOS integrated circuit is annealed after deposition of the SiN dielectric layer and the SiN dielectric layer is removed from at least a part of the integrated circuit.
摘要翻译：一种用于形成具有不降低PMOS晶体管的高Si-H / N-H键比的NMOS晶体管的应力记忆增强的拉伸SiN应力层的方法。 CMOS集成电路通过NMOS源极和漏极注入而不是通过NMOS源极和漏极退火进行处理。沉积SiN电介质层，使得FTIR光谱中Si-H峰与N-H峰的面积比大于7，并且SiN电介质的拉伸应力大于150MPa。在沉积SiN电介质层之后对CMOS集成电路进行退火，并且从集成电路的至少一部分去除SiN介电层。

7. 发明申请

US20060189048A1 Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer 有权
标题翻译：使用封端的多晶硅层减少PMOS器件的掺杂剂扩散的方法来应变NMOS器件
公开(公告)号：US20060189048A1
公开(公告)日：2006-08-24
申请号：US11060841
申请日：2005-02-18
申请人： Manoj Mehrotra , Lahir Adam , Song Zhao , Mahalingam Nandakumar
发明人： Manoj Mehrotra , Lahir Adam , Song Zhao , Mahalingam Nandakumar
IPC分类号： H01L21/84
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/6659 , H01L29/7843 , Y10S438/902
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.
摘要翻译：本发明通过提供制造方法来促进半导体制造，所述方法对设备的沟道区域施加拉伸应变，同时减轻不期望的掺杂剂扩散，这降低了器件性能。源极/漏极区形成在PMOS区（102）的有源区中。执行第一热处理，其激活所形成的源极/漏极区域和在注入的掺杂剂（104）中的驱动。随后，在NMOS区域（106）的有源区域中形成源极/漏极区域。然后，在器件（108）上形成封端的多晶硅层。执行第二热处理（110），其使得封端的多晶硅层引入器件的沟道区域的应变。由于第一热处理，减少了在第二热处理期间不期望的掺杂剂扩散，特别是不期望的p型掺杂剂扩散。

8. 发明授权

US06822297B2 Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness 有权
标题翻译：额外的n型LDD /袋式注入，用于改善短沟道NMOS ESD稳健性
公开(公告)号：US06822297B2
公开(公告)日：2004-11-23
申请号：US09876292
申请日：2001-06-07
申请人： Mahalingam Nandakumar , Song Zhao , Youngmin Kim
发明人： Mahalingam Nandakumar , Song Zhao , Youngmin Kim
IPC分类号： H01L2362
CPC分类号： H01L29/6659 , H01L27/0266 , H01L29/1083 , H01L29/7833
摘要： A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions. According to the invention, these regions of higher p-type resistivity are created after gate definition by an ion implant of compensating n-doping, such as arsenic or phosphorus, using the same photomask already used for implants creating the extended source and drain and the pockets of enhanced p-doping. In an ESD event, these regions of higher resistivity increase the current gain of the parasitic lateral npn bipolar transistor and thus raise the current It2, which initiates the thermal breakdown with its destructive localized heating, thereby improving ESD robustness.
摘要翻译： p阱中的短沟道NMOS晶体管具有n源极和n沟道，每个包含延伸到晶体管栅极的浅区域，每个侧面由隔离区域横向限定并由沟道停止区域垂直地限定以及从栅极凹陷的较深区域，并且当反向偏置时都具有耗尽区域。浅区域部分地被增强的p掺杂注入口袋包围。晶体管还在这些增强的p掺杂区域中具有比半导体其余部分高的p电阻率的另一区域。这些区域大致从相应的浅区域的内部边界横向延伸到相应的凹陷区域的内部边界，并且从刚好在源极和漏极的耗尽区域的深度的深度垂直地延伸到接近通道停止区域的顶部。根据本发明通过使用已经用于形成扩展的源极和漏极的植入物的相同的光掩模，通过补偿n掺杂的离子注入（例如砷或磷）在栅极定义之后产生这些较高p型电阻率的区域，在ESD事件中，这些具有较高电阻率的区域增加了寄生横向npn双极晶体管的电流增益，从而提高了电流It2，从而使其具有破坏性的局部加热引起热击穿，从而提高了ESD鲁棒性。

9. 发明授权

US08993575B2 [1,3,4] oxadiazole derivative and application thereof 有权
标题翻译： [1,3,4]恶二唑衍生物及其应用
公开(公告)号：US08993575B2
公开(公告)日：2015-03-31
申请号：US14008693
申请日：2012-04-01
申请人： Guisen Zhang , Yin Chen , Xiangqing Xu , Bifeng Liu , Xiaojun Feng , Song Zhao , Shicheng Liu , Minquan Yu , Yu Lan , Yinli Qiu
发明人： Guisen Zhang , Yin Chen , Xiangqing Xu , Bifeng Liu , Xiaojun Feng , Song Zhao , Shicheng Liu , Minquan Yu , Yu Lan , Yinli Qiu
IPC分类号： A61K31/496 , A61K31/454 , A61K31/4545 , C07D413/14 , C07D417/12 , C07D417/14
CPC分类号： C07D417/12 , C07D413/14 , C07D417/14
摘要： The present invention belongs to the medicinal chemistry field, and specifically discloses a [1,3,4]oxadiazole derivative with the structure of general formula (I) and pharmaceutically acceptable salt thereof. The compound can be used to prepare a medicine for preventing or treating a disease of the central nervous system.
摘要翻译：本发明属于药物化学领域，具体公开了具有通式（I）结构的[1,3,4]恶二唑衍生物及其药学上可接受的盐。该化合物可用于制备用于预防或治疗中枢神经系统疾病的药物。

10. 发明授权

US08717405B2 Method and device for generating 3D panoramic video streams, and videoconference method and device 有权
标题翻译：用于生成3D全景视频流的方法和设备，以及视频会议方法和设备
公开(公告)号：US08717405B2
公开(公告)日：2014-05-06
申请号：US13172193
申请日：2011-06-29
申请人： Kai Li , Yuan Liu , Jing Wang , Honghong Su , Song Zhao
发明人： Kai Li , Yuan Liu , Jing Wang , Honghong Su , Song Zhao
IPC分类号： H04N7/14
CPC分类号： H04N21/4223 , H04N7/15 , H04N13/243 , H04N21/42203 , H04N21/4788
摘要： A method and a device for generating 3-dimensional (3D) panoramic video streams, a videoconference method, and a videoconference device are disclosed. The method includes: obtaining depth information of at least two video images; obtaining image data in multiple depth positions from a corresponding video image according to the depth information of each video image; stitching data of the video images according to the obtained image data in multiple depth positions, and generating 3D panoramic video streams. The technical solution of the present invention provides users with high-resolution 3D panoramic seamless telepresence conference video images based on different display modes of different display devices.
摘要翻译：公开了一种用于产生三维（3D）全景视频流的方法和装置，视频会议方法和视频会议装置。该方法包括：获取至少两个视频图像的深度信息; 根据每个视频图像的深度信息从相应的视频图像获得多个深度位置的图像数据; 根据所获得的多个深度位置的图像数据拼接视频图像的数据，并生成3D全景视频流。本发明的技术方案为用户提供了基于不同显示设备的不同显示模式的高分辨率3D全景无线远程呈现会议视频图像。

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