专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07029967B2 Silicide method for CMOS integrated circuits 有权
标题翻译： CMOS集成电路的硅化法
公开(公告)号：US07029967B2
公开(公告)日：2006-04-18
申请号：US10896599
申请日：2004-07-21
申请人： Song Zhao , Sue E. Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald S. Miles , Duofeng Yue , Lance S. Robertson
发明人： Song Zhao , Sue E. Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald S. Miles , Duofeng Yue , Lance S. Robertson
IPC分类号： H01L21/8238 , H01L21/331
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.
摘要翻译：描述了在源区和漏区（160,170）中形成金属硅化物区域的方法。在源极和漏极区域（160,170）的热退火之前，将锗注入到与栅极结构（60,70）相邻形成的侧壁结构（90,95）附近的半导体衬底中。植入的锗物质在半导体衬底中的位置将与源区和漏区（160,170）重叠。在源极和漏极区域（160,170）的热退火之后，注入的锗防止形成金属硅化物尖峰。

2. 发明授权

US07208409B2 Integrated circuit metal silicide method 有权
标题翻译：集成电路金属硅化物法
公开(公告)号：US07208409B2
公开(公告)日：2007-04-24
申请号：US11073982
申请日：2005-03-07
申请人： Jiong-Ping Lu , Duofeng Yue , Xiaozhan Liu , Donald S. Miles , Lance S. Robertson
发明人： Jiong-Ping Lu , Duofeng Yue , Xiaozhan Liu , Donald S. Miles , Lance S. Robertson
IPC分类号： H01L21/44 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L29/7833
摘要： Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.
摘要翻译：含氟区域（70）形成在MOS晶体管的源区和漏区（60）中。在含氟区域（70）和源极和漏极区域（60）之上形成金属层（90）。金属层与下面的含氟区域反应以形成金属硅化物。

3. 发明授权

US07335595B2 Silicide formation using a low temperature anneal process 有权
标题翻译：使用低温退火工艺的硅化物形成
公开(公告)号：US07335595B2
公开(公告)日：2008-02-26
申请号：US11155151
申请日：2005-06-17
申请人： Lance S. Robertson , Jiong-Ping Lu , Donald S. Miles
发明人： Lance S. Robertson , Jiong-Ping Lu , Donald S. Miles
IPC分类号： H01L21/44
CPC分类号： H01L27/0629 , H01L21/28518 , H01L28/24 , H01L29/7833
摘要： A silicide 160 is formed in exposed silicon on a semiconductor wafer 10 by a method that includes forming a thin interface layer 140 over the semiconductor wafer 10 and performing a first low temperature anneal to create the silicide 160. The method further includes removing an unreacted portion of the interface layer 140 and performing a second low temperature anneal to complete the formation of a low resistance silicide 160.
摘要翻译：通过包括在半导体晶片10上形成薄界面层140并执行第一低温退火以形成硅化物160的方法，在半导体晶片10上的暴露的硅中形成硅化物160.该方法还包括去除未反应部分并且执行第二低温退火以完成形成低电阻硅化物160。

4. 发明授权

US07422967B2 Method for manufacturing a semiconductor device containing metal silicide regions 有权
标题翻译：制造含有金属硅化物区域的半导体器件的方法
公开(公告)号：US07422967B2
公开(公告)日：2008-09-09
申请号：US11127669
申请日：2005-05-12
申请人： Juanita DeLoach , Lindsey H. Hall , Lance S. Robertson , Jiong-Ping Lu , Donald S. Miles
发明人： Juanita DeLoach , Lindsey H. Hall , Lance S. Robertson , Jiong-Ping Lu , Donald S. Miles
IPC分类号： H01L21/3205
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/665
摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).
摘要翻译：本发明提供一种制造半导体器件的方法。在本发明的一个实施例中，但不限于，用于制造半导体器件的方法包括在衬底（110）上形成栅极结构（120）并且在靠近栅极的衬底（110）中形成源/漏区（190）结构（120）。该方法还包括在源极/漏极区（190）中使用含氟等离子体，使用小于约75瓦特的功率电平形成含氟区域（220），在基底（110）上形成金属层（310），以及含氟区域（220），并且使金属层（310）与含氟区域（220）反应以在源极/漏极区域（190）中形成金属硅化物区域（410）。

5. 发明授权

US07232744B2 Method for implanting dopants within a substrate by tilting the substrate relative to the implant source 有权
标题翻译：通过使衬底相对于植入源倾斜来在衬底内注入掺杂剂的方法
公开(公告)号：US07232744B2
公开(公告)日：2007-06-19
申请号：US10956583
申请日：2004-10-01
申请人： Said Ghneim , James D. Bernstein , Lance S. Robertson , Jiejie Xu , Jeffrey Loewecke
发明人： Said Ghneim , James D. Bernstein , Lance S. Robertson , Jiejie Xu , Jeffrey Loewecke
IPC分类号： H01L21/265
CPC分类号： H01L21/26586 , H01J2237/31701 , H01L21/823814 , Y10S438/914
摘要： The present invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device. The method for implanting a dopant, among other steps, including tilting a substrate (310) located on or over an implant platen (305) about an axis in a first direction with respect to an implant source (320) and implanting a portion of an implant dose within the substrate (310) tilted in the first direction. The method further includes tilting the substrate (310) having already been tilted in the first direction about the axis in a second opposite direction, and implanting at least a portion of the implant dose within the substrate (310) tilted in the second opposite direction.
摘要翻译：本发明提供了一种用于在衬底中注入掺杂剂的方法和用于制造半导体器件的方法。用于植入掺杂剂的方法以及其它步骤包括使位于植入物台板（305）上方或上方的衬底（310）相对于植入源（320）沿着第一方向的轴线倾斜并植入一部分在第一方向上倾斜的衬底（310）内的植入剂量。该方法还包括使已经在第一方向上沿第一方向倾斜的衬底（310）沿着第二相反方向围绕该轴线倾斜，并且将植入剂量的至少一部分植入衬底（310）内沿第二相反方向倾斜。

6. 发明授权

US07385202B2 Divergent charged particle implantation for improved transistor symmetry 有权
标题翻译：用于改善晶体管对称性的发散带电粒子注入
公开(公告)号：US07385202B2
公开(公告)日：2008-06-10
申请号：US11006185
申请日：2004-12-07
申请人： James D. Bernstein , Lance S. Robertson , Said Ghneim , Jiejie Xu , Jeffrey Loewecke
发明人： James D. Bernstein , Lance S. Robertson , Said Ghneim , Jiejie Xu , Jeffrey Loewecke
IPC分类号： G01N23/00 , G21K7/00
CPC分类号： H01L29/78 , H01J2237/31701 , H01L21/26513 , H01L29/66575
摘要： The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for implanting charged particles in a substrate, among other steps, includes projecting a beam of charged particles (320) to a substrate (330), the beam of charged particles (320) having a given beam divergence, and forming a diverged beam of charged particles (360) by subjecting the beam of charged particles (320) to an energy field (350), thereby causing the beam of charged particles (320) to have a larger beam divergence. The method then desires implanting the diverged beam of charged particles (360) into the substrate (330).
摘要翻译：本发明提供了一种用于将带电粒子注入基板的方法和用于制造集成电路的方法。用于将带电粒子注入衬底的方法以及其他步骤包括将带电粒子束（320）投射到衬底（330），具有给定光束发散的带电粒子束（320），并形成发散光束的带电粒子（360）通过使带电粒子束（320）经受能量场（350），从而使带电粒子束（320）具有较大的光束发散。该方法然后期望将发散的带电粒子束（360）植入衬底（330）中。

7. 发明申请

US20070281433A1 A METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMPLANT 有权
标题翻译：一种减少使用抑制植入物进行椎间盘切除的方法
公开(公告)号：US20070281433A1
公开(公告)日：2007-12-06
申请号：US11422221
申请日：2006-06-05
申请人： Martin Mollat , Tathagata Chatterjee , Henry L. Edwards , Lance S. Robertson , Richard B. Irwin , Binghua Hu
发明人： Martin Mollat , Tathagata Chatterjee , Henry L. Edwards , Lance S. Robertson , Richard B. Irwin , Binghua Hu
IPC分类号： H01L21/20
CPC分类号： H01L29/866 , H01L21/26506 , H01L29/66098
摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.
摘要翻译：本发明提供一种制造半导体器件的方法。在一个实施例中，制造半导体器件的方法包括制造齐纳二极管的方法，其包括在衬底内形成掺杂阱并在衬底内形成抑制注入。用于制造齐纳二极管的方法还可以包括在衬底内形成阴极和阳极，其中抑制植入物位于掺杂阱附近并且被配置为减少穿透位错。

8. 发明授权

US06699771B1 Process for optimizing junctions formed by solid phase epitaxy 有权
标题翻译：用于优化由固相外延形成的结的方法
公开(公告)号：US06699771B1
公开(公告)日：2004-03-02
申请号：US10213837
申请日：2002-08-06
申请人： Lance S. Robertson
发明人： Lance S. Robertson
IPC分类号： H01L2176
CPC分类号： H01L21/2022 , H01L21/26506 , H01L21/26513 , H01L29/6659
摘要： A method of forming a semiconductor device includes forming at least one amorphous region within an at least partially formed semiconductor device. The method also includes implanting a halogen species in the amorphous region of the at least partially formed semiconductor device. The method further includes doping at least a portion of the at least one amorphous region to form at least one junction within the at least partially formed semiconductor device. The method also includes performing solid phase epitaxial re-growth to activate the doped portion of the at least one amorphous region of the at least partially formed semiconductor device.
摘要翻译：形成半导体器件的方法包括在至少部分形成的半导体器件内形成至少一个非晶区域。该方法还包括在至少部分形成的半导体器件的非晶区域中注入卤素物质。所述方法还包括掺杂所述至少一个非晶区域的至少一部分以在所述至少部分形成的半导体器件内形成至少一个结。该方法还包括执行固相外延再生长以激活至少部分形成的半导体器件的至少一个非晶区域的掺杂部分。

9. 发明授权

US07638415B2 Method for reducing dislocation threading using a suppression implant 有权
标题翻译：使用抑制植入物减少位错螺纹的方法
公开(公告)号：US07638415B2
公开(公告)日：2009-12-29
申请号：US12267216
申请日：2008-11-07
申请人： Martin Mollat , Tathagata Chatterjee , Henry L. Edwards , Lance S. Robertson , Richard B. Irwin , Binghua Hu
发明人： Martin Mollat , Tathagata Chatterjee , Henry L. Edwards , Lance S. Robertson , Richard B. Irwin , Binghua Hu
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L29/866 , H01L21/26506 , H01L29/66098
摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.
摘要翻译：本发明提供一种制造半导体器件的方法。在一个实施例中，制造半导体器件的方法包括一种制造齐纳二极管的方法，其包括在衬底（210）内形成掺杂阱（240），并在衬底（210）内形成抑制注入（420））。用于制造齐纳二极管的方法还可以包括在衬底（210）内形成阴极（620）和阳极（520），其中抑制注入（420）位于掺杂阱（240）附近，并且被配置为减少穿线脱臼

10. 发明授权

US07466009B2 Method for reducing dislocation threading using a suppression implant 有权
标题翻译：使用抑制植入物减少位错螺纹的方法
公开(公告)号：US07466009B2
公开(公告)日：2008-12-16
申请号：US11422221
申请日：2006-06-05
申请人： Martin Mollat , Tathagata Chatterjee , Henry L. Edwards , Lance S. Robertson , Richard B. Irwin , Binghua Hu
发明人： Martin Mollat , Tathagata Chatterjee , Henry L. Edwards , Lance S. Robertson , Richard B. Irwin , Binghua Hu
IPC分类号： H01L29/93 , H01L23/62
CPC分类号： H01L29/866 , H01L21/26506 , H01L29/66098
摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.
摘要翻译：本发明提供一种制造半导体器件的方法。在一个实施例中，制造半导体器件的方法包括制造齐纳二极管的方法，其包括在衬底内形成掺杂阱并在衬底内形成抑制注入。用于制造齐纳二极管的方法还可以包括在衬底内形成阴极和阳极，其中抑制植入物位于掺杂阱附近并且被配置为减少穿透位错。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式