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    • 3. 发明授权
    • Design method and system for optimum performance in integrated circuits that use power management
    • 使用电源管理的集成电路中的最佳性能设计方法和系统
    • US07216310B2
    • 2007-05-08
    • US10993815
    • 2004-11-19
    • Amitava ChatterjeeDavid Barry ScottTheodore W. HoustonSong ZhaoShaoping TangZhiqiang Wu
    • Amitava ChatterjeeDavid Barry ScottTheodore W. HoustonSong ZhaoShaoping TangZhiqiang Wu
    • G06F17/50G11C5/14H03K3/01G05F1/10
    • G06F17/505
    • The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
    • 本发明提供一种设计电路的方法(100)。 该方法包括指定(105)存储晶体管和逻辑晶体管的设计参数,并选择(110)存储晶体管的测试保持模式偏置电压。 所述方法还包括在所述测试保持模式偏置电压下确定(115)保持模式漏电流和所述设计参数的第一关系,并获得(120)所述有源模式驱动电流与所述设计参数的第二关系。 使用第一和第二关系(125)来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。 该方法还包括调整(130)测试保持模式偏置电压,并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。
    • 4. 发明申请
    • Design method and system for optimum performance in integrated circuits that use power management
    • 使用电源管理的集成电路中的最佳性能设计方法和系统
    • US20050149887A1
    • 2005-07-07
    • US10993815
    • 2004-11-19
    • Amitava ChatterjeeDavid ScottTheodore HoustonSong ZhaoShaoping TangZhiqiang Wu
    • Amitava ChatterjeeDavid ScottTheodore HoustonSong ZhaoShaoping TangZhiqiang Wu
    • G06F17/50
    • G06F17/505
    • The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
    • 本发明提供一种设计电路的方法(100)。 该方法包括指定(105)存储晶体管和逻辑晶体管的设计参数,并选择(110)存储晶体管的测试保持模式偏置电压。 所述方法还包括在所述测试保持模式偏置电压下确定(115)保持模式漏电流和所述设计参数的第一关系,并获得(120)所述有源模式驱动电流与所述设计参数的第二关系。 使用第一和第二关系(125)来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。 该方法还包括调整(130)测试保持模式偏置电压,并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。