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1. 发明授权

US07029967B2 Silicide method for CMOS integrated circuits 有权
标题翻译： CMOS集成电路的硅化法
公开(公告)号：US07029967B2
公开(公告)日：2006-04-18
申请号：US10896599
申请日：2004-07-21
申请人： Song Zhao , Sue E. Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald S. Miles , Duofeng Yue , Lance S. Robertson
发明人： Song Zhao , Sue E. Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald S. Miles , Duofeng Yue , Lance S. Robertson
IPC分类号： H01L21/8238 , H01L21/331
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.
摘要翻译：描述了在源区和漏区（160,170）中形成金属硅化物区域的方法。在源极和漏极区域（160,170）的热退火之前，将锗注入到与栅极结构（60,70）相邻形成的侧壁结构（90,95）附近的半导体衬底中。植入的锗物质在半导体衬底中的位置将与源区和漏区（160,170）重叠。在源极和漏极区域（160,170）的热退火之后，注入的锗防止形成金属硅化物尖峰。

2. 发明申请

US20060019478A1 Silicide method for CMOS integrated circuits 有权
公开(公告)号：US20060019478A1
公开(公告)日：2006-01-26
申请号：US10896599
申请日：2004-07-21
申请人： Song Zhao , Sue Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald Miles , Duofeng Yue , Lance Robertson
发明人： Song Zhao , Sue Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald Miles , Duofeng Yue , Lance Robertson
IPC分类号： H01L21/28
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.

3. 发明申请

US20140001526A1 Analog Floating-Gate Capacitor with Improved Data Retention in a Silicided Integrated Circuit 有权
标题翻译：在硅化集成电路中具有改进的数据保持性的模拟浮栅电容器
公开(公告)号：US20140001526A1
公开(公告)日：2014-01-02
申请号：US13534865
申请日：2012-06-27
申请人： Kaiping Liu , Amitava Chatterjee , Imran Mahmood Khan
发明人： Kaiping Liu , Amitava Chatterjee , Imran Mahmood Khan
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L29/66181 , H01L27/0629 , H01L27/0805 , H01L27/11558 , H01L28/60
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.
摘要翻译：集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。由氮化硅顶层下面的二氧化硅层构成的硅化物阻挡膜阻止在电极上形成硅化物包层，而诸如多晶硅对金属电容器的集成电路中的其它多晶硅结构是硅化物 - 包裹在硅化之后，在剩余的多晶硅结构上沉积电容器电介质，随后形成上部金属板。

4. 发明授权

US08779550B2 Analog floating-gate capacitor with improved data retention in a silicided integrated circuit 有权
标题翻译：模拟浮栅电容器，在硅化集成电路中具有改进的数据保留能力
公开(公告)号：US08779550B2
公开(公告)日：2014-07-15
申请号：US13534865
申请日：2012-06-27
申请人： Kaiping Liu , Amitava Chatterjee , Imran Mahmood Khan
发明人： Kaiping Liu , Amitava Chatterjee , Imran Mahmood Khan
IPC分类号： H01L27/108
CPC分类号： H01L29/66181 , H01L27/0629 , H01L27/0805 , H01L27/11558 , H01L28/60
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.
摘要翻译：集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。由氮化硅顶层下面的二氧化硅层构成的硅化物阻挡膜阻止在电极上形成硅化物包层，而诸如多晶硅对金属电容器的集成电路中的其它多晶硅结构是硅化物 - 包裹在硅化之后，在剩余的多晶硅结构上沉积电容器电介质，随后形成上部金属板。

5. 发明授权

US07216310B2 Design method and system for optimum performance in integrated circuits that use power management 有权
标题翻译：使用电源管理的集成电路中的最佳性能设计方法和系统
公开(公告)号：US07216310B2
公开(公告)日：2007-05-08
申请号：US10993815
申请日：2004-11-19
申请人： Amitava Chatterjee , David Barry Scott , Theodore W. Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
发明人： Amitava Chatterjee , David Barry Scott , Theodore W. Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
IPC分类号： G06F17/50 , G11C5/14 , H03K3/01 , G05F1/10
CPC分类号： G06F17/505
摘要： The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
摘要翻译：本发明提供一种设计电路的方法（100）。该方法包括指定（105）存储晶体管和逻辑晶体管的设计参数，并选择（110）存储晶体管的测试保持模式偏置电压。所述方法还包括在所述测试保持模式偏置电压下确定（115）保持模式漏电流和所述设计参数的第一关系，并获得（120）所述有源模式驱动电流与所述设计参数的第二关系。使用第一和第二关系（125）来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。该方法还包括调整（130）测试保持模式偏置电压，并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。

6. 发明申请

US20050149887A1 Design method and system for optimum performance in integrated circuits that use power management 有权
标题翻译：使用电源管理的集成电路中的最佳性能设计方法和系统
公开(公告)号：US20050149887A1
公开(公告)日：2005-07-07
申请号：US10993815
申请日：2004-11-19
申请人： Amitava Chatterjee , David Scott , Theodore Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
发明人： Amitava Chatterjee , David Scott , Theodore Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
摘要翻译：本发明提供一种设计电路的方法（100）。该方法包括指定（105）存储晶体管和逻辑晶体管的设计参数，并选择（110）存储晶体管的测试保持模式偏置电压。所述方法还包括在所述测试保持模式偏置电压下确定（115）保持模式漏电流和所述设计参数的第一关系，并获得（120）所述有源模式驱动电流与所述设计参数的第二关系。使用第一和第二关系（125）来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。该方法还包括调整（130）测试保持模式偏置电压，并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。

7. 发明申请

US20120275207A1 SRAM CELL PARAMETER OPTIMIZATION 有权
标题翻译： SRAM单元参数优化
公开(公告)号：US20120275207A1
公开(公告)日：2012-11-01
申请号：US13097370
申请日：2011-04-29
申请人： Theodore W. Houston , Puneet Kohli , Amitava Chatterjee
发明人： Theodore W. Houston , Puneet Kohli , Amitava Chatterjee
IPC分类号： G11C11/412 , H01L21/8244
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207
摘要： An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.
摘要翻译：具有SRAM单元的集成电路包括一对交叉耦合的反相器，其中第一驱动器和负载晶体管被连接以提供第一存储节点和第二驱动器以及连接到第二存储节点的负载晶体管。 SRAM单元还包括由至少一个字线控制并分别连接在第一位线和第一存储节点之间的第一和第二通过栅极晶体管以及第二位线和第二存储节点; 其中第一驱动晶体管阈值电压不同于第二驱动晶体管阈值电压，并且第一和第二驱动器阈值电压中的一个不同于通过栅极晶体管阈值电压。或者，第一和第二驱动晶体管的阈值电压不同于对称的通过栅极晶体管阈值电压。另外，提供了具有SRAM单元的集成电路的制造方法。

8. 发明授权

US08053322B2 Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom 有权
标题翻译：用于减小沟槽边缘处栅极电介质薄化的外延沉积工艺及其集成电路
公开(公告)号：US08053322B2
公开(公告)日：2011-11-08
申请号：US12344995
申请日：2008-12-29
申请人： Vladimir F. Drobny , Amitava Chatterjee , Phillipp Steinmann , Rick Wise
发明人： Vladimir F. Drobny , Amitava Chatterjee , Phillipp Steinmann , Rick Wise
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/76229 , H01L21/823481 , H01L21/823878 , H01L29/1087 , H01L29/66651
摘要： A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface. The epitaxial comprising silicon layer is oxidized to convert at least a portion into a thermally grown silicon oxide layer, wherein the thermally grown silicon oxide layer provides at least a portion of a gate dielectric layer for at least one of said plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges. Fabrication of the IC is then completed.
摘要翻译：一种制造集成电路（IC）及其IC的方法，包括多个金属氧化物半导体（MOS）晶体管，其栅极电介质薄膜在沟槽隔离/半导体边缘处具有减小的栅极电介质薄化和拐角锐化，用于通常为500至5000埃厚的栅极电介质层。该方法包括提供具有包含硅的表面的衬底。在衬底中形成多个电介质填充沟槽隔离区。包括表面的硅在其周边与沟槽隔离区形成沟槽隔离有源区边缘。沉积外延硅层，其中包含硅层的外延形成在包含硅的表面上。包含硅层的外延被氧化以将至少一部分转化成热生长的氧化硅层，其中热生长的氧化硅层为所述多个MOS晶体管中的至少一个提供至少一部分栅极电介质层。在栅极电介质上形成图案化的栅极电极层，其中图案化的栅极电极层在沟槽隔离有源区域边缘中的至少一个上延伸。然后完成IC的制造。

9. 发明申请

US20100274506A1 METHOD FOR MEASURING INTERFACE TRAPS IN THIN GATE OXIDE MOSFETS 有权
标题翻译：用于测量薄壁氧化物MOSFET中的界面行为的方法
公开(公告)号：US20100274506A1
公开(公告)日：2010-10-28
申请号：US12831122
申请日：2010-07-06
申请人： Tathagata Chatterjee , Amitava Chatterjee
发明人： Tathagata Chatterjee , Amitava Chatterjee
IPC分类号： G01R31/26 , G06F19/00
CPC分类号： G01R31/2621
摘要： A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.
摘要翻译：一种用于测量MOSFET中的接口陷阱的方法，包括测量在预定频率范围内各种频率的脉冲波形的电荷泵浦电流，产生所测量的电荷泵浦电流相对于预定频率范围的绘制点，确定接口总数通过计算通过绘制点的最佳拟合线的斜率参与电荷泵浦电流的陷阱。

10. 发明申请

US20090134471A1 SEMICONDUCTOR INTERCONNECT 有权
公开(公告)号：US20090134471A1
公开(公告)日：2009-05-28
申请号：US11944861
申请日：2007-11-26
申请人： Amitava Chatterjee , Howard Tigelaar , Victor Sutcliffe
发明人： Amitava Chatterjee , Howard Tigelaar , Victor Sutcliffe
IPC分类号： H01L23/532 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/53238 , H01L23/53257 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.
摘要翻译：一个实施例涉及包括至少一个半导体器件的集成电路。集成电路包括与半导体器件的第一端子相关联的第一接触。第一触点跨越介电层并且将第一端子耦合到在集成电路上水平传送信号的互连线，其中互连线具有第一组成。集成电路还包括与半导体器件的第二端子相关联的第二触点。第二接触跨越电介质层并将第二端子耦合到通孔连接到的着陆焊盘，其中着陆焊盘具有不同于第一组成的第二组成。还公开了其它电路和方法。

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