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1. 发明授权

US07689303B2 Data transfer in audio codec controllers 有权
标题翻译：音频编解码器控制器中的数据传输
公开(公告)号：US07689303B2
公开(公告)日：2010-03-30
申请号：US10259716
申请日：2002-09-27
申请人： Norbert Ziep , Thomas Berndt
发明人： Norbert Ziep , Thomas Berndt
IPC分类号： G06F17/00 , G06F13/00
CPC分类号： G10H7/002 , G10H2240/275
摘要： An audio codec control technique is provided with improved multichannel data ordering capabilities. An audio codec controller comprises a first interface unit for performing data transfer to and from an audio codec, a second interface unit for performing data transfer from an external memory, and a data buffer for buffering data received from the external memory via the second interface unit. The controller further comprises a capture register for receiving from the data buffer data requested by the audio codec, and temporarily storing the received data. The first interface unit is connected to receive temporarily stored data from the capture register. The operation of the audio codec controller may be done in several operational modes including 2, 4, and 6-channel full-rate and half-rate modes.
摘要翻译：音频编解码器控制技术具有改进的多通道数据排序功能。音频编解码器控制器包括用于执行到音频编解码器的数据传输和从外部存储器执行数据传输的第二接口单元的第一接口单元和用于缓冲经由第二接口单元从外部存储器接收的数据的数据缓冲器。该控制器还包括捕捉寄存器，用于从数据缓冲器接收由音频编解码器请求的数据，并临时存储所接收的数据。第一接口单元被连接以从捕获寄存器接收临时存储的数据。音频编解码器控制器的操作可以在包括2,4和6声道全速率和半速率模式的几种操作模式中完成。

2. 发明申请

US20020134218A1 MUSICAL COMPUTER KEYBOARD APPARATUS AND METHOD 失效
标题翻译：音乐电脑键盘设备及方法
公开(公告)号：US20020134218A1
公开(公告)日：2002-09-26
申请号：US09816939
申请日：2001-03-23
发明人： Dean VanDruff
IPC分类号： G10H001/26
CPC分类号： G10H1/20 , G10H1/34 , G10H2220/231 , G10H2240/275
摘要： An apparatus and method to change the mode of computer keyboard use from alpha-numeric language orientation to become a musical input keyboard where the keys change meaning for this purpose is provided. The apparatus and method implements a unique musical mapping for a standard computer keyboard such that the musical notes that are most often used in musical composition are mapped to keys of a home row of the standard keyboard. Musical notes that are the next most often utilized in musical composition are mapped to keys in the rows above and below the home row. All other musical notes are mapped based on their relative probability of being used in combination with the notes mapped in the home row and the rows above and below the home row.
摘要翻译：提供了一种用于将计算机键盘使用模式从字母数字语言方向改变为用于此目的而改变键的音乐输入键盘的装置和方法。该装置和方法实现了用于标准计算机键盘的唯一的音乐映射，使得最常用于音乐作品的音符被映射到标准键盘的主行的键。音乐作品中最常使用的音符是映射到主列上下方向的键。所有其他音符都是基于它们与在主行中映射的音符和主行上下行的组合使用的相对概率进行映射的。

3. 发明公开

EP0842437A1 VCC LEVEL DETECTION CIRCUIT 失效
标题翻译： VCC值检测电路
公开(公告)号：EP0842437A1
公开(公告)日：1998-05-20
申请号：EP95939770.0
申请日：1995-11-02
申请人： ADVANCED MICRO DEVICES, INC.
发明人： BREHMER, Geoffrey, E. , SCHNIZLEIN, Paul, G.
IPC分类号： G01R19 , G05F1 , G10H7 , H03K5 , H03K19
CPC分类号： H03K19/018585 , G01R19/16528 , G01R19/16538 , G05F1/465 , G10H7/004 , G10H2230/035 , G10H2240/275
摘要： A supply voltage detect circuit is described which generates a control signal indicating the status of VCC to be at 5.0 or 3.3 volts. This control signal is used to generate analog reference signals used by A/D and/or D/A circuitry in an audio processing integrated circuit and by other circuitry to control clock frequencies or current drive. An input buffer is also described which is configurable depending on whether a 5.0 or 3.3 volt supply voltage is present. The input buffer includes two input buffer circuits. The output of a first input buffer circuit is output as valid data when VCC equals 5.0 volts. The output of the second input buffer circuit is output as valid data when VCC equals 3.3 volts.

4. 发明公开

EP0910827A3 CIRCUITS, SYSTEM, AND METHODS FOR PROCESSING MULTIPLE DATA STREAMS 失效
标题翻译：电路，系统和方法用于处理多个数据流
公开(公告)号：EP0910827A3
公开(公告)日：2002-08-28
申请号：EP98911371.7
申请日：1998-02-09
申请人： Cirrus Logic, Inc
发明人： NORTH, Gregory, Allen , GEPHARDT, Douglas , BARNETTE, James, D. , AUSTIN, James, D. , HABAN, Scott, Thomas , DAVID, Thomas, Saroshan , KIRCHER, Brian, Christopher
IPC分类号： G06F17/10
CPC分类号： G10H7/002 , G06F3/162 , G10H2240/275

5. 发明公开

EP0910827A2 CIRCUITS, SYSTEM, AND METHODS FOR PROCESSING MULTIPLE DATA STREAMS 失效
标题翻译：电路，系统和方法用于处理多个数据流
公开(公告)号：EP0910827A2
公开(公告)日：1999-04-28
申请号：EP98911371
申请日：1998-02-09
申请人： CIRRUS LOGIC INC
发明人： NORTH GREGORY ALLEN , GEPHARDT DOUGLAS , BARNETTE JAMES D , AUSTIN JAMES D , HABAN SCOTT THOMAS , DAVID THOMAS SAROSHAN , KIRCHER BRIAN CHRISTOPHER
IPC分类号： G10H7/00 , G06F17/10
CPC分类号： G10H7/002 , G06F3/162 , G10H2240/275
摘要： An audio information processing subsystem (200) is disclosed which includes a stream processor (100) for simultaneously processing multiple streams of audio data. Processing subsystem (200) also includes a program memory (202) coupled to stream processor (100) for storing instructions for controlling processing system (200) and a data memory (203/204) also coupled to stream processor (100). Additionally, a direct memory access circuitry (208) is provided for controlling direct memory accesses to a selected one of program memory (202) and data memory (203/204).

6. 发明申请

WO9835301A3 CIRCUITS, SYSTEM, AND METHODS FOR PROCESSING MULTIPLE DATA STREAMS 审中-公开
标题翻译：用于处理多个数据流的电路，系统和方法
公开(公告)号：WO9835301A3
公开(公告)日：1999-04-01
申请号：PCT/US9802319
申请日：1998-02-09
申请人： CIRRUS LOGIC INC
发明人： NORTH GREGORY ALLEN , GEPHARDT DOUGLAS , BARNETTE JAMES D , AUSTIN JAMES D , HABAN SCOTT THOMAS , DAVID THOMAS SAROSHAN , KIRCHER BRIAN CHRISTOPHER
IPC分类号： G10H7/00 , G06F17/10 , G06F5/06 , G06F7/544 , G06F9/302 , G06F9/355 , G06F9/46 , G06F11/34 , G06F13/28 , G06F13/40 , G06F15/78
CPC分类号： G10H7/002 , G06F3/162 , G10H2240/275
摘要： An audio information processing subsystem (200) is disclosed which includes a stream processor (100) for simultaneously processing multiple streams of audio data. Processing subsystem (200) also includes a program memory (202) coupled to stream processor (100) for storing instructions for controlling processing system (200) and a data memory (203/204) also coupled to stream processor (100). Additionally, a direct memory access circuitry (208) is provided for controlling direct memory accesses to a selected one of program memory (202) and data memory (203/204).
摘要翻译：公开了一种音频信息处理子系统（200），其包括用于同时处理多个音频数据流的流处理器（100）。处理子系统（200）还包括耦合到流处理器（100）的程序存储器（202），用于存储用于控制处理系统（200）的指令和还耦合到流处理器（100）的数据存储器（203/204）。另外，提供了直接存储器访问电路（208），用于控制对程序存储器（202）和数据存储器（203/204）中所选择的一个的直接存储器访问。

7. 发明申请

WO1997036283A1 COMPUTER SYSTEM AND METHOD FOR PERFORMING WAVETABLE MUSIC SYNTHESIS 审中-公开
标题翻译：用于执行音乐音乐合成的计算机系统和方法
公开(公告)号：WO1997036283A1
公开(公告)日：1997-10-02
申请号：PCT/US1997002505
申请日：1997-02-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , GULICK, Dale, E.
IPC分类号： G10H07/00
CPC分类号： G10H7/004 , G10H2240/275
摘要： A computer system and method for performing wavetable music synthesis uses system memory (202) to store wavetable data (222) and minimizes audio infidelity introduced by wavetable data access latency. The system comprises a system memory (202) which stores wavetable data (222) an I/O bus (206) coupled to the system memory (202), and a system audio device (220). The system audio device (220) comprises an I/O bus interface (330) coupled to the I/O bus (206), a synthesizer (340, 350) which generates sounds in response to the wavetable data (222) a plurality of buffers (360) coupled to the I/O bus interface (330) and to the synthesizer (350) for buffering the wavetable data from the system memory (202), and a buffer manager (370) coupled to the I/O bus interface (330), the synthesizer (340, 350), and the plurality of buffers (360). The buffer manager (370) manages transfers of the wavetable data (222) from the system memory (202) to the buffers (360) and from the buffers (360) to the synthesizer (350). The synthesizer (340, 350) generates a request to the buffer manager (370) for wavetable samples. If the samples do not reside in the buffers (360) and the buffer manager (370) is unable to retrieve the samples from the system memory (202) within a desired frame time, the synthesizer (340, 350) outputs surrogate values until the samples become available. The synthesizer (340, 350) calculates the surrogate values so as to avoid producing audible artifacts in the sound generated by the synthesizer. The synthesizer (340, 350) calculates the surrogate values according to one of two methods. The first method is to simply output the last valid value calculated by the synthesizer (340, 350). The second method is to ramp the value toward zero at a rate defined as the fastest rate which does not produce audible artifacts.
摘要翻译：用于执行波表音乐合成的计算机系统和方法使用系统存储器（202）来存储波形数据（222）并且使由波形数据访问等待时间引入的音频不忠度最小化。该系统包括存储波形数据（222）的系统存储器（222），耦合到系统存储器（202）的I / O总线（206）和系统音频设备（220）。系统音频设备（220）包括耦合到I / O总线（206）的I / O总线接口（330），合成器（340,350），响应于波形数据（222）产生多个耦合到I / O总线接口（330）的缓冲器（360）和用于从系统存储器（202）缓冲波形数据的合成器（350）;以及耦合到I / O总线接口（330），合成器（340,350）和多个缓冲器（360）。缓冲器管理器（370）管理波形数据（222）从系统存储器（202）到缓冲器（360）以及从缓冲器（360）到合成器（350）的传送。合成器（340,350）向缓冲器管理器（370）生成用于波表样本的请求。如果样本不驻留在缓冲器（360）中，并且缓冲器管理器（370）不能在期望的帧时间内从系统存储器（202）检索样本，则合成器（340,350）输出代理值直到样品可用。合成器（340,350）计算代理值，以避免在由合成器产生的声音中产生可听见的伪影。合成器（340,350）根据两种方法之一计算代理值。第一种方法是简单地输出由合成器计算的最后一个有效值（340,350）。第二种方法是将值以零定义为不产生可听见的伪像的最快速率的速率向零斜坡。

8. 发明申请

WO1997031363A1 PC AUDIO SYSTEM WITH FREQUENCY COMPENSATED WAVETABLE DATA 审中-公开
标题翻译：具有频率补偿波形数据的PC音频系统
公开(公告)号：WO1997031363A1
公开(公告)日：1997-08-28
申请号：PCT/US1997002811
申请日：1997-02-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , HEWITT, Larry
IPC分类号： G10H07/02
CPC分类号： G10H7/004 , G10H7/02 , G10H2230/031 , G10H2240/275
摘要： The PC audio circuit (10) described interfaces with and provides audio enhancement to a host personal computer of the type including a central processor, system memory and a system bus. The PC audio circuit (10) includes a digital signal processor (DSP) (16) for processing wavetable data and generating digital audio signals for a plurality of voices. The wavetable data is stored in the host computer's system memory and transferred in portions, as needed by the DSP (16) to a smaller, low-cost cache memory (22) included with the PC audio circuit (10). The DSP (16) processes several frames of data samples for an active voice before processing another voice. Processing in this manner alleviates concerns about the percentage use of system bus bandwidth and the maximum allowable system bus latency. These concerns are further alleviated by deriving frequency compensated wavetable data and storing it in system memory to be retrieved by the DSP (16) for generating digital audio signals having high frequency ratios. Digital audio signals generated for each active voice are accumulated in cache memory (22). When the digital audio signals for all active voices have been accumulated, the accumulated data is transmitted from the cache memory (22) to an external digital-to-analog converter. Since wavetable data is stored in system memory, the cache memory (22) is smaller and less expensive than the local memory in prior art PC audio circuits. Thus, the described PC audio circuit (10) has a lower overall cost.
摘要翻译：描述的PC音频电路（10）与包括中央处理器，系统存储器和系统总线的主机个人计算机接口并提供音频增强。 PC音频电路（10）包括用于处理波形数据并产生多个语音的数字音频信号的数字信号处理器（DSP）（16）。波形数据被存储在主计算机的系统存储器中，并且根据DSP（16）的需要，以包括在PC音频电路（10）中的较小的，低成本的高速缓冲存储器（22）的一部分传送。在处理另一个声音之前，DSP（16）处理主动语音的多个数据采样帧。以这种方式进行的处理减轻了对系统总线带宽的使用百分比和最大允许系统总线延迟的担忧。通过导出频率补偿波形数据并将其存储在由DSP（16）检索以产生具有高频率的数字音频信号的系统存储器中，进一步减轻了这些问题。为每个活动语音生成的数字音频信号被累积在高速缓存存储器（22）中。当用于所有活动语音的数字音频信号已被累积时，累积的数据从高速缓冲存储器（22）发送到外部数模转换器。由于波形数据存储在系统存储器中，高速缓冲存储器（22）比现有技术的PC音频电路中的本地存储器更小且更便宜。因此，所描述的PC音频电路（10）具有较低的总成本。

9. 发明授权

EP0882286B1 PC AUDIO SYSTEM WITH FREQUENCY COMPENSATED WAVETABLE DATA 失效
标题翻译：音频系统与频率补偿的波形数据PC
公开(公告)号：EP0882286B1
公开(公告)日：2000-06-21
申请号：EP97907795.5
申请日：1997-02-21
申请人： Advanced Micro Devices, Inc.
发明人： HEWITT, Larry
IPC分类号： G10H7/02
CPC分类号： G10H7/004 , G10H7/02 , G10H2230/031 , G10H2240/275
摘要： The PC audio circuit (10) described interfaces with and provides audio enhancement to a host personal computer of the type including a central processor, system memory and a system bus. The PC audio circuit (10) includes a digital signal processor (DSP) (16) for processing wavetable data and generating digital audio signals for a plurality of voices. The wavetable data is stored in the host computer's system memory and transferred in portions, as needed by the DSP (16) to a smaller, low-cost cache memory (22) included with the PC audio circuit (10). The DSP (16) processes several frames of data samples for an active voice before processing another voice. Processing in this manner alleviates concerns about the percentage use of system bus bandwidth and the maximum allowable system bus latency. These concerns are further alleviated by deriving frequency compensated wavetable data and storing it in system memory to be retrieved by the DSP (16) for generating digital audio signals having high frequency ratios. Digital audio signals generated for each active voice are accumulated in cache memory (22). When the digital audio signals for all active voices have been accumulated, the accumulated data is transmitted from the cache memory (22) to an external digital-to-analog converter. Since wavetable data is stored in system memory, the cache memory (22) is smaller and less expensive than the local memory in prior art PC audio circuits. Thus, the described PC audio circuit (10) has a lower overall cost.

10. 发明公开

EP0882286A1 PC AUDIO SYSTEM WITH FREQUENCY COMPENSATED WAVETABLE DATA 失效
标题翻译：音频系统与频率补偿的波形数据PC
公开(公告)号：EP0882286A1
公开(公告)日：1998-12-09
申请号：EP97907795.0
申请日：1997-02-21
申请人： Advanced Micro Devices, Inc.
发明人： HEWITT, Larry
IPC分类号： G10H7
CPC分类号： G10H7/004 , G10H7/02 , G10H2230/031 , G10H2240/275
摘要： The PC audio circuit (10) described interfaces with and provides audio enhancement to a host personal computer of the type including a central processor, system memory and a system bus. The PC audio circuit (10) includes a digital signal processor (DSP) (16) for processing wavetable data and generating digital audio signals for a plurality of voices. The wavetable data is stored in the host computer's system memory and transferred in portions, as needed by the DSP (16) to a smaller, low-cost cache memory (22) included with the PC audio circuit (10). The DSP (16) processes several frames of data samples for an active voice before processing another voice. Processing in this manner alleviates concerns about the percentage use of system bus bandwidth and the maximum allowable system bus latency. These concerns are further alleviated by deriving frequency compensated wavetable data and storing it in system memory to be retrieved by the DSP (16) for generating digital audio signals having high frequency ratios. Digital audio signals generated for each active voice are accumulated in cache memory (22). When the digital audio signals for all active voices have been accumulated, the accumulated data is transmitted from the cache memory (22) to an external digital-to-analog converter. Since wavetable data is stored in system memory, the cache memory (22) is smaller and less expensive than the local memory in prior art PC audio circuits. Thus, the described PC audio circuit (10) has a lower overall cost.

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