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1. 发明授权

US08891277B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08891277B2
公开(公告)日：2014-11-18
申请号：US13313186
申请日：2011-12-07
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： H01L27/2481 , G11C5/02 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2213/31 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/78 , H01L21/768 , H01L27/2454 , H01L29/66666 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1608
摘要： According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.
摘要翻译：根据一个实施例，存储器件包括第一至第三互连，存储器单元和选择器。第一至第三互连分别沿着第一至第三方向设置。存储单元包括形成在第三互连件的第一方向上彼此面对的两个侧表面上的可变电阻层。选择器将第三互连与第一互连耦合。其中一个选择器包括一个半导体层，该半导体层设置在相互连接的第三互连中的一个和第一互连中的相关一个之间，以及形成在半导体层的在第一方向上彼此相对的两个侧表面上的栅极之间的栅极绝缘膜。

2. 发明授权

US08498142B2 Resistance change memory 有权
标题翻译：电阻变化记忆
公开(公告)号：US08498142B2
公开(公告)日：2013-07-30
申请号：US13072029
申请日：2011-03-25
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0033 , G11C2013/0092 , G11C2213/71 , G11C2213/72
摘要： A memory includes memory cells each includes a resistance change element and a diode, and each memory cell between one of row lines and one of column lines, a first decoder which selects one of the row lines as a selected row line, a second decoder which selects one of the column lines as a selected column line, a voltage pulse generating circuit which generates a voltage pulse, a voltage pulse shaping circuit which makes a rise time and a fall time of the voltage pulse longer, and a control circuit which applies the voltage pulse outputting from the voltage pulse shaping circuit to unselected column lines except the selected column line, and which applies a fixed potential to unselected row lines except the selected row line, in a data writing to a memory cell which is provided between the selected row line and the selected column line.
摘要翻译：存储器包括各自包括电阻变化元件和二极管的存储单元，以及行线和列线之一之间的每个存储单元，选择行行之一作为所选行行的第一解码器，第二解码器，选择列线之一作为选择的列线，产生电压脉冲的电压脉冲发生电路，使电压脉冲的上升时间和下降时间更长的电压脉冲整形电路以及施加电压脉冲的控制电路电压脉冲从电压脉冲整形电路输出到除了所选列线之外的未选择的列线，并且在设置在所选择的行之间的存储单元的数据写入中将固定电位施加到除所选行行之外的未选行行行和所选列行。

3. 发明授权

US08391048B2 Non-volatile semiconductor memory device including memory cells with a variable resistor 有权
标题翻译：包括具有可变电阻器的存储单元的非易失性半导体存储器件
公开(公告)号：US08391048B2
公开(公告)日：2013-03-05
申请号：US12846198
申请日：2010-07-29
申请人： Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
发明人： Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
IPC分类号： G11C11/00
CPC分类号： G11C13/0061 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0092
摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.
摘要翻译：根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。根据本发明的实施例的一个方面的非易失性半导体存储器件还包括一个控制器，用于选择给定的一个存储单元，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给选择的存储单元。擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

4. 发明授权

US08320157B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08320157B2
公开(公告)日：2012-11-27
申请号：US12876637
申请日：2010-09-07
申请人： Reika Ichihara , Takayuki Tsukamoto , Hiroshi Kanno , Kenichi Murooka
发明人： Reika Ichihara , Takayuki Tsukamoto , Hiroshi Kanno , Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2213/13 , G11C2213/34 , G11C2213/72
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。存储单元阵列包括多个第一布线，与多条第一布线相交的多条第二布线，以及多个存储单元，设置在多个第一布线和第二布线的交点处，每个包括非欧姆元件和串联连接的可变电阻元件。控制电路选择多个存储单元中的一个，产生用于从所选存储单元擦除数据的擦除脉冲，并将擦除脉冲提供给所选存储单元。控制电路通过在反向偏置方向上向非欧姆元件施加擦除脉冲的电压来执行数据擦除。

5. 发明授权

US08222626B2 Semiconductor memory device, method of manufacturing the same, and method of screening the same 有权
标题翻译：半导体存储器件及其制造方法及其筛选方法
公开(公告)号：US08222626B2
公开(公告)日：2012-07-17
申请号：US12705010
申请日：2010-02-12
申请人： Mitsuru Sato , Masanori Komura , Hiroshi Kanno , Kenichi Murooka
发明人： Mitsuru Sato , Masanori Komura , Hiroshi Kanno , Kenichi Murooka
IPC分类号： H01L45/00
CPC分类号： H01L27/1021 , G11C29/832 , G11C29/88 , G11C2213/72 , H01L27/24 , H01L29/0657 , H01L29/868
摘要： A semiconductor memory device includes first and second memory cells each including a variable resistance element and a diode and having a pillar shape, and an insulating layer provided between the first memory cell and the second memory cell and including a void. A central portion of the diode has a smaller width than widths of upper and lower portions of the diode.
摘要翻译：一种半导体存储器件，包括：第一和第二存储单元，每个存储单元包括可变电阻元件和二极管，并具有柱形;以及绝缘层，设置在第一存储单元和第二存储单元之间并且包括空隙。二极管的中心部分的宽度比二极管的上部和下部的宽度小。

6. 发明授权

US08084830B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08084830B2
公开(公告)日：2011-12-27
申请号：US12556005
申请日：2009-09-09
申请人： Hiroshi Kanno , Kenichi Murooka , Jun Hirota , Hideyuki Tabata
发明人： Hiroshi Kanno , Kenichi Murooka , Jun Hirota , Hideyuki Tabata
IPC分类号： H01L27/11
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/1027
摘要： The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si1-xGex (0
摘要翻译：存储单元位于第一布线和第二布线之间的相应交点处。每个存储单元具有串联连接的整流元件和可变电阻元件。整流元件包括p型第一半导体区域和n型第二半导体区域。第一半导体区域至少部分地由硅 - 锗混合物（Si1-xGex（0

7. 发明授权

US08848418B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08848418B2
公开(公告)日：2014-09-30
申请号：US13327065
申请日：2011-12-15
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： H01L45/1233 , G11C8/10 , G11C13/0002 , G11C13/0023 , G11C2213/71 , G11C2213/72 , H01L27/2463 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1608
摘要： A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2
摘要翻译：根据一个实施例的半导体存储器件包括由多个行线和列线构成的存储单元阵列，所述多个行线和列线彼此相交，并且从布置在行线和列线的每个交点处的多个存储单元组成，并且每个包括可变电阻元件。在假设行数为N的情况下，假设列数为M，当存储单元中存在的一个存储单元中的电池电流为选择电压的一半时的电流比当将选择电压施加到一个存储器单元时，将存储单元中的一个施加到流过该存储单元中的一个存储单元的单元电流，则关系M2 <2×N×k 满意。

8. 发明授权

US08320156B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08320156B2
公开(公告)日：2012-11-27
申请号：US12695512
申请日：2010-01-28
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C13/0007 , G11C8/08 , G11C8/12 , G11C13/0004 , G11C13/0023 , G11C2213/71
摘要： A semiconductor memory device includes a plurality of first wirings; a plurality of second wirings; a plurality of memory cells positioned at respective intersections of the first wirings and the second wirings, each of the memory cells having a variable resistance element and a selective element connected to the variable resistance element in series; a first selection portion selecting the first wiring; a second selection portion selecting the second wiring; and a power source portion applying predetermined selected-wiring-voltages to a selected first wiring being selected by the first selection portion and a selected second wiring being selected by the second selection portion, respectively, and applying predetermined unselected-wiring-voltages to unselected first wirings other than the selected first wiring and unselected second wirings other than the selected second wiring, respectively. A resistance element having a predetermined resistance value is provided between the power source portion and the unselected first and second wirings.
摘要翻译：半导体存储器件包括多个第一配线; 多个第二布线; 多个存储单元，位于第一布线和第二布线的相应交点处，每个存储单元具有可变电阻元件和与可变电阻元件串联连接的选择元件; 选择第一布线的第一选择部分; 选择第二布线的第二选择部分; 以及电源部，分别对由所述第一选择部选择的所选择的第一布线和由所述第二选择部选择的所选择的第二布线分别施加预定的选择布线电压，并将预定的未选择布线电压施加到未选择的第一布线电压除了所选择的第一布线以外的布线和除所选择的第二布线以外的未选择的第二布线。在电源部分和未选择的第一和第二布线之间设置具有预定电阻值的电阻元件。

9. 发明申请

US20120075913A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120075913A1
公开(公告)日：2012-03-29
申请号：US13235431
申请日：2011-09-18
申请人： Tetsuji KUNITAKE , Kenichi Murooka
发明人： Tetsuji KUNITAKE , Kenichi Murooka
IPC分类号： G11C11/21
CPC分类号： G11C13/0004 , G11C8/08 , G11C8/14 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0069 , G11C2013/0076 , G11C2213/71
摘要： A nonvolatile semiconductor memory device includes: a memory cell array which has a plurality of first lines, a plurality of second lines intersecting the plurality of first lines and a plurality of memory cells which store an electrically rewritable resistance value as data in a non-volatile manner; a first decoder which is connected to one ends of the plurality of first lines and selects the first lines; a second decoder which is connected to the plurality of second lines and selects the second lines; and a voltage applying circuit which is connected to one of the first and second decoders and which applies a predetermined voltage between the first and second lines selected by the first and second decoders. The second decoder sequentially selects the second lines in a direction from the other ends to the one ends of the first lines.
摘要翻译：非易失性半导体存储器件包括：存储单元阵列，其具有多个第一线，与多条第一线相交的多条第二线，以及存储电可重写电阻值作为非易失性数据的多个存储单元方式; 第一解码器，其连接到所述多个第一线的一端并选择所述第一线; 第二解码器，连接到所述多个第二线并选择所述第二线; 以及电压施加电路，其连接到第一和第二解码器中的一个，并且在由第一和第二解码器选择的第一和第二线之间施加预定电压。第二解码器从第一行的另一端到一端的方向依次选择第二行。

10. 发明申请

US20110026299A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA WRITE/DATA ERASE THEREIN 有权
标题翻译：非易失性半导体存储器件及数据写入/数据擦除方法
公开(公告)号：US20110026299A1
公开(公告)日：2011-02-03
申请号：US12713667
申请日：2010-02-26
申请人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka
发明人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka
IPC分类号： G11C11/00 , G11C5/14 , G11C7/00
CPC分类号： G11C5/025 , G11C13/0007 , G11C13/003 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： A nonvolatile semiconductor memory device comprises: a plurality of first lines; a plurality of second lines; a plurality of memory cells each disposed at each of crossing-points of the first lines and the second lines and each comprising a variable resistor and a bi-directional diode; and a voltage control circuit configured to control a voltage of selected one of the first lines, unselected ones of the first lines, selected one of the second lines, and unselected ones of the second lines, respectively. The variable resistor is configured to change its resistance value depending on a polarity of a voltage applied thereto. The voltage control circuit is configured to apply a voltage pulse to the selected one of the first lines and to connect a capacitor of a certain capacitance to one end of the selected one of the second lines.
摘要翻译：非易失性半导体存储器件包括：多条第一线; 多条第二线; 多个存储单元，每个存储单元分别设置在第一线和第二线的交叉点的每一个处，并且每个存储单元包括可变电阻器和双向二极管; 以及电压控制电路，被配置为分别控制所选择的第一行，未选择的第一行，所选择的第二行和未选择的第二行中的一个的电压。可变电阻器被配置为根据施加到其的电压的极性来改变其电阻值。电压控制电路被配置为向所选择的第一线中的一个施加电压脉冲，并且将一定电容的电容器连接到所选择的一条第二线路的一端。

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