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1. 发明申请

US20190252025A1 PHYSICAL SECURE ERASE OF SOLID STATE DRIVES 审中-公开
公开(公告)号：US20190252025A1
公开(公告)日：2019-08-15
申请号：US16392252
申请日：2019-04-23
申请人： Western Digital Technologies, Inc.
发明人： Zhenlei Z. Shen , Nian Niles Yang , Gautham Reddy
IPC分类号： G11C16/16 , G11C16/08
CPC分类号： G11C16/16 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C29/44 , G11C29/52 , G11C29/765 , G11C29/832
摘要： Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.

2. 发明授权

US09905316B2 Efficient sense amplifier shifting for memory redundancy 有权
公开(公告)号：US09905316B2
公开(公告)日：2018-02-27
申请号：US15225744
申请日：2016-08-01
申请人： QUALCOMM Incorporated
发明人： Sonia Ghosh , Changho Jung
IPC分类号： G11C7/00 , G11C29/00 , G11C7/06 , G11C7/22
CPC分类号： G11C29/781 , G11C7/065 , G11C7/22 , G11C29/702 , G11C29/832 , G11C29/846 , G11C29/848
摘要： A memory includes a plurality of columns and a redundant column. The memory includes a plurality of multiplexers corresponding to the plurality of columns. Depending upon the location of a defect, the multiplexers are configured to select for their corresponding column or an immediately-subsequent column to their corresponding column.

3. 发明授权

US09722335B2 Dual in line memory module (DIMM) connector 有权
公开(公告)号：US09722335B2
公开(公告)日：2017-08-01
申请号：US14270156
申请日：2014-05-05
申请人： QUALCOMM Incorporated
发明人： Robert Walter Berry, Jr. , Ryan Joseph Pennington , Joab Daniel Henderson , Divya Kumar
IPC分类号： G06F11/07 , H01R12/70 , G06F11/20 , G06F13/16 , G06F13/40
CPC分类号： H01R12/7076 , G06F11/008 , G06F11/07 , G06F11/2094 , G06F13/1668 , G06F13/409 , G11C5/04 , G11C29/781 , G11C29/832
摘要： An enhanced dual in line memory module (DIMM) connector includes internal conductive paths that provide access to signaling on standard conductive paths to an industry standard DIMM. The internal conductive paths are coupled in series or in parallel with the standard conductive paths through the connector. Interposer circuitry, such as control circuitry and or supplemental memory circuitry, may be incorporated on or within the connector. The interposer circuitry may include field effect transistor (FET) switching circuitry configured to selectively decouple a defective dynamic random memory (DRAM) on a DIMM from a conductive path to a memory controller and couple a substitute DRAM to the conductive paths in its place.

4. 发明申请

US20170092682A1 IMAGE SENSOR, STACKED IMAGE SENSOR, IMAGE PROCESSING APPARATUS, AND METHOD OF FABRICATING IMAGE SENSOR CHIP PACKAGE 审中-公开
公开(公告)号：US20170092682A1
公开(公告)日：2017-03-30
申请号：US15274077
申请日：2016-09-23
申请人： Min-jun CHOI
发明人： Min-jun CHOI
IPC分类号： H01L27/146 , G11C29/00 , H04N5/357 , H04N5/378 , H01L21/66 , G11C17/16 , G11C17/18
CPC分类号： H01L27/14638 , G11C17/16 , G11C17/18 , G11C29/44 , G11C29/78 , G11C29/785 , G11C29/832 , H01L22/20 , H01L22/22 , H01L27/14609 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H04N5/3575 , H04N5/378 , H04N5/379
摘要： An image sensor includes a pixel array and a peripheral circuit. The peripheral circuit is electrically connected to the pixel array and includes a logic block and at least one redundancy block to replace the logic block when the logic block is a defective block.

5. 发明授权

US09263111B2 Sub-block disabling in 3D memory 有权
公开(公告)号：US09263111B2
公开(公告)日：2016-02-16
申请号：US14682762
申请日：2015-04-09
申请人： Micron Technology, Inc.
发明人： Chang Wan Ha
IPC分类号： G11C29/00 , G11C8/12 , G11C8/06 , G11C8/08
CPC分类号： G11C8/12 , G11C8/06 , G11C8/08 , G11C11/5621 , G11C16/08 , G11C16/20 , G11C29/00 , G11C29/04 , G11C29/76 , G11C29/765 , G11C29/78 , G11C29/832
摘要： Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.

6. 发明授权

US09251864B2 System and method for providing voltage supply protection in a memory device 有权
标题翻译：在存储器件中提供电压保护的系统和方法
公开(公告)号：US09251864B2
公开(公告)日：2016-02-02
申请号：US13605129
申请日：2012-09-06
申请人： Jan Otterstedt , Wolf Allers , Mihail Jefremow , Edvin Paparisto , Leonardo Castro , Thomas Kern
发明人： Jan Otterstedt , Wolf Allers , Mihail Jefremow , Edvin Paparisto , Leonardo Castro , Thomas Kern
IPC分类号： G11C29/04 , G11C29/02 , G11C5/14
CPC分类号： G11C29/83 , G11C5/143 , G11C29/02 , G11C29/04 , G11C29/832
摘要： The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.
摘要翻译：本发明涉及一种电子存储器系统，更具体地说，涉及一种用于在存储器件中提供电压保护的系统，以及一种在存储器件中提供电压保护的方法。根据实施例，提供了一种用于在存储器件中提供电压保护的系统，该系统包括一个存储器阵列，该存储器阵列包括布置在多组存储器单元中的多个存储单元，以及多个限流元件，其中每组存储器单元与至少一个限流元件相关联。

7. 发明授权

US09063874B2 Apparatus, system, and method for wear management 有权
标题翻译：磨损管理的装置，系统和方法
公开(公告)号：US09063874B2
公开(公告)日：2015-06-23
申请号：US13844338
申请日：2013-03-15
申请人： Fusion-io, Inc.
发明人： Hao Zhong , Ned D. Plasson , Robert Wood , Jea Woong Hyun , Hairong Sun
IPC分类号： G06F11/00 , G06F11/10 , G06F12/02 , G06F11/14 , G11C29/00 , G11C16/04 , G11C16/34 , G11C29/42 , G11C29/04 , G11C29/12 , G06F11/30
CPC分类号： G06F11/1008 , G06F11/108 , G06F11/141 , G06F11/3034 , G06F11/3055 , G06F12/0246 , G06F2211/109 , G11C16/04 , G11C16/3418 , G11C16/3422 , G11C16/349 , G11C16/3495 , G11C29/42 , G11C29/82 , G11C29/832 , G11C29/88 , G11C2029/0411 , G11C2029/1208
摘要： A storage module is configured to determine a health metric of a storage division of a solid-state storage medium. The health metric may comprise a combination of factors, including, but not limited to: wear level, performance (e.g., program time, erase time, and the like), error rate, and the like. A wear level module may configure storage operations to reduce the wear rate of storage divisions having poor health metrics and/or heath metrics that are degrading more quickly than other storage divisions. Reducing wear rate may include deferring grooming operations, delaying use for storage operations, temporarily retiring the storage division, or the like. Storage divisions may be brought back into service at normal use rates in response determining that other portions of the storage media have been worn to the point that they exhibit similar health and/or reliability characteristics.
摘要翻译：存储模块被配置为确定固态存储介质的存储分区的健康度量。健康度量可以包括因素的组合，包括但不限于：磨损水平，性能（例如，程序时间，擦除时间等），错误率等。磨损水平模块可以配置存储操作以降低具有差的健康度量和/或健康度量的存储部门的磨损率，其比其他存储部门更快地劣化。降低磨损率可能包括推迟修饰操作，延迟存储操作的使用，暂时停止存储部门等。存储部门可以以正常使用率被恢复使用，以响应确定存储介质的其他部分已经磨损到它们表现出类似的健康和/或可靠性特征的点。

8. 发明授权

US09007860B2 Sub-block disabling in 3D memory 有权
标题翻译：子块在3D存储器中禁用
公开(公告)号：US09007860B2
公开(公告)日：2015-04-14
申请号：US13781097
申请日：2013-02-28
申请人： Micron Technology, Inc.
发明人： Chang Wan Ha
IPC分类号： G11C8/00 , G11C29/00 , G11C8/06
CPC分类号： G11C8/12 , G11C8/06 , G11C8/08 , G11C11/5621 , G11C16/08 , G11C16/20 , G11C29/00 , G11C29/04 , G11C29/76 , G11C29/765 , G11C29/78 , G11C29/832
摘要： Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.
摘要翻译：一些实施例涉及与存储器单元的块相关联的装置和方法。存储器单元的块可以包括存储器单元的两个或更多个子块。一个这样的子块可以包括包括选择晶体管的存储单元的垂直串。装置可以包括子块禁止电路。子块禁止电路可以包括内容寻址存储器。内容可寻址存储器可以接收包括块地址和子块地址的地址。如果接收到的地址包括块地址和与标记子块相关联的子块地址，则内容可寻址存储器可以输出信号以禁用标记子块。子块禁止电路还可以包括多个驱动器，以基于该信号来驱动一个或多个选择晶体管。描述其他装置和方法。

9. 发明申请

US20140192602A1 DEFECTIVE MEMORY COLUMN REPLACEMENT WITH LOAD ISOLATION 有权
标题翻译：有缺陷的记忆柱替换与负载隔离
公开(公告)号：US20140192602A1
公开(公告)日：2014-07-10
申请号：US13733948
申请日：2013-01-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Silke Penth , Raphael Polig , Tobias Werner , Alexander Woerner
IPC分类号： G11C29/04
CPC分类号： G11C29/04 , G11C11/41 , G11C29/785 , G11C29/832
摘要： Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells.
摘要翻译：本发明的示例性实施例公开了一种用于将一组存储器单元替换为存储器中的存储器单元的缺陷组的方法和系统。在一个步骤中，示例性实施例将具有到冗余存储器单元组的信号路径的信号路径替换到一组缺陷存储器单元。在另一步骤中，示例性实施例将来自由信号路径施加的负载的冗余组的信号路径隔离到更换的有缺陷的存储器单元组。

10. 发明申请

US20140050003A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND DRIVING METHOD OF VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器件和可变电阻非易失性存储器件的驱动方法
公开(公告)号：US20140050003A1
公开(公告)日：2014-02-20
申请号：US14113054
申请日：2012-05-24
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa
IPC分类号： G11C29/00 , G11C13/00
CPC分类号： G11C29/70 , G11C13/004 , G11C13/0069 , G11C29/52 , G11C29/808 , G11C29/832 , G11C29/883 , G11C2029/5006 , G11C2213/15 , G11C2213/71 , G11C2213/72
摘要： A stable operation is implemented by reducing an abnormal current. A variable resistance nonvolatile memory device includes: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of bit lines and one of word lines, and the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied; and a detection circuit that detects a faulty memory cell that is in a second low resistance state where a resistance value is lower than a resistance value in a first low resistance state. Both the bit line and the word line that are connected to the faulty memory cell detected by the detection circuit are fixed in the inactive state.
摘要翻译：通过减少异常电流实现稳定运行。可变电阻非易失性存储器件包括：存储单元阵列，其具有各自包括串联连接的可变电阻元件和电流导向元件的存储单元，每个存储单元位于位之一的三维交叉点线路和字线之一，并且当施加超过预定阈值电压的电压时，假定当前的导向元件正在导通; 以及检测电路，其检测处于第二低电阻状态的电阻值低于第一低电阻状态下的电阻值的故障存储单元。连接到由检测电路检测到的故障存储单元的位线和字线均固定在不活动状态。

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