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91. 发明授权

US07225384B2 Method for controlling turbo decoding time in a high-speed packet data communication system 有权
标题翻译：用于在高速分组数据通信系统中控制turbo解码时间的方法
公开(公告)号：US07225384B2
公开(公告)日：2007-05-29
申请号：US10698405
申请日：2003-11-03
申请人： Jin-Woo Heo , Min-Goo Kim , Jae-Hong Lee , Sang-Hyuck Ha
发明人： Jin-Woo Heo , Min-Goo Kim , Jae-Hong Lee , Sang-Hyuck Ha
IPC分类号： H04L1/18
CPC分类号： H04L1/0051 , H04L1/0066 , H04L1/0072 , H04L1/1812 , H04L1/1848
摘要： A method for controlling a turbo decoding time in a high-speed packet data communication system. In a mobile communication system which receives a control message from a packet data control channel, at the same time receives packet data from the packet data channel, performs demodulating and turbo-decoding of the packet data during a predetermined response (ACK/NAK) time delay using a demodulation result of the packet data control channel, creates a result of the turbo decoding in the form of a response (ACK/NAK) signal, and transmits the turbo decoding result, the method includes the steps of a) demodulating the control message when simultaneously receiving the control message and the packet data, and demodulating and decoding the packet data, and b) if the response time delay expires while decoding the packet data, interrupting a decoding operation of the turbo decoder.
摘要翻译：一种用于在高速分组数据通信系统中控制turbo解码时间的方法。在从分组数据控制信道接收控制消息的移动通信系统中，同时从分组数据信道接收分组数据，在预定的响应（ACK / NAK）时间内进行分组数据的解调和turbo解码使用分组数据控制信道的解调结果进行延迟，以响应（ACK / NAK）信号的形式产生turbo解码的结果，并发送turbo解码结果，该方法包括以下步骤：a）解调控制消息，同时接收控制消息和分组数据，解调和解码分组数据，以及b）如果响应时间延迟在解码分组数据时到期，则中断Turbo解码器的解码操作。

92. 发明授权

US07200796B2 Apparatus for generating codes in communication system 有权
标题翻译：用于在通信系统中生成代码的装置
公开(公告)号：US07200796B2
公开(公告)日：2007-04-03
申请号：US10680815
申请日：2003-10-07
申请人： Min-Goo Kim , Jae-Sung Jang
发明人： Min-Goo Kim , Jae-Sung Jang
IPC分类号： H03M13/03 , H03M13/00
CPC分类号： H04L1/0066 , G11B20/22 , H03M13/27 , H03M13/2771 , H03M13/2957 , H03M13/296 , H03M13/6306 , H03M13/635 , H03M13/6356 , H03M13/6362 , H03M13/6381 , H03M13/6387 , H04L1/0009 , H04L1/0041 , H04L1/0059 , H04L1/0065 , H04L1/0068 , H04L1/0069 , H04L1/0071 , H04L1/08 , H04L1/1812 , H04L1/1819 , H04L1/1874
摘要： A QCTC (Quasi-Complementary Turbo Code) generating apparatus having a turbo encoder for generating an information symbol sequence and a plurality of parity symbol sequences by encoding the information symbol sequence; a channel interleaver for individually interleaving the symbol sequences, generating new parity symbol sequences by multiplexing the symbols of parity symbol sequences with the same priority levels, and serially concatenating the information symbol sequence and the new parity symbol sequences; and a QCTC generator for generating a sub-code with a given code rate by recursively selecting a predetermined number of symbols from the concatenated symbol sequence at a given starting position.
摘要翻译：具有用于通过对信息符号序列进行编码来生成信息符号序列和多个奇偶校验符号序列的Turbo编码器的QCTC（准互补Turbo码）生成装置; 用于单独地交织符号序列的信道交织器，通过对具有相同优先级的奇偶校验符号序列的符号进行多路复用生成新的奇偶符号序列，以及串行级联信息符号序列和新的奇偶校验符号序列; 以及QCTC发生器，用于通过在给定的开始位置从所述级联的符号序列递归地选择预定数量的符号来产生具有给定码率的子码。

93. 发明申请

US20060284690A1 Phase locked loop, phase detecting method for the phase locked loop, and receiver using the same 有权
标题翻译：锁相环，锁相环的相位检测方法和使用该锁相环的接收机
公开(公告)号：US20060284690A1
公开(公告)日：2006-12-21
申请号：US11453852
申请日：2006-06-16
申请人： Hee-Jin Roh , Su-Jin Yoon , Min-Goo Kim
发明人： Hee-Jin Roh , Su-Jin Yoon , Min-Goo Kim
IPC分类号： H03L7/00
CPC分类号： H03L7/085 , G01R25/005 , H04L7/033
摘要： A Phase Locked Loop (PLL) is provided for improving acquisition performance in an acquisition state, while preventing performance degradation in a steady state under a low SNR environment, during phase detection, a phase detecting method for the PLL, and a receiver using the same. The PLL determines a period to which an input signal belongs according to the input signal and a feedback signal, outputs an error signal corresponding to the input signal by using a formula (or algorithm) set for the determined period, oscillates a predetermined frequency signal according to the error signal, and feeds back the oscillated signal.
摘要翻译：提供锁相环（PLL），用于在采集状态下改善采集性能，同时在相位检测期间防止在低SNR环境下的稳定状态下的性能下降，PLL的相位检测方法和使用该锁相环的接收机。 PLL根据输入信号和反馈信号确定输入信号所属的周期，通过使用为所确定的周期设置的公式（或算法）输出与输入信号相对应的误差信号，根据到错误信号，并反馈振荡的信号。

94. 发明申请

US20060268673A1 Method, apparatus, and system for transmitting and receiving data in a digital broadcasting system using a single frequency network 审中-公开
标题翻译：用于在使用单频网络的数字广播系统中发送和接收数据的方法，装置和系统
公开(公告)号：US20060268673A1
公开(公告)日：2006-11-30
申请号：US11406602
申请日：2006-04-19
申请人： Hee-Jin Roh , Kyung-Ha Lee , Suk-Jin Jung , Min-Goo Kim
发明人： Hee-Jin Roh , Kyung-Ha Lee , Suk-Jin Jung , Min-Goo Kim
IPC分类号： H04J11/00
CPC分类号： H04L27/2602 , H04H20/67 , H04H60/23 , H04H60/50
摘要： A method, apparatus, and system for transmitting and receiving data in a digital broadcasting system based on Orthogonal Frequency Division Multiplexing (OFDM) are provided. A transmitter frames input bit information in a predetermined bit unit, maps the framed input bit information to a transmitter identification indicator (TII) using a predefined number of orthogonal sets, and modulates the TII to an OFDM symbol to transmit the OFDM symbol. A receiver demodulates an OFDM symbol, detects a TII symbol from a predefined orthogonal signal set, demaps predetermined bits from the TII, and concatenates the demapped bits in a predetermined period unit to output bit information. Therefore, the TII can be stably received as a conditional access signal for distinguishing a broadcasting network and a relay network in the digital broadcasting system.
摘要翻译：提供了一种在基于正交频分复用（OFDM）的数字广播系统中发送和接收数据的方法，装置和系统。发送机以预定比特单位帧输入比特信息，使用预定数量的正交组将成帧的输入比特信息映射到发射机识别指示符（TII），并将TII调制为OFDM符号以发送OFDM符号。接收机解调OFDM符号，从预定义的正交信号集中检测TII符号，从TII解映射预定比特，并以预定周期单元连接解映射比特以输出比特信息。因此，可以稳定地接收TII作为用于区分数字广播系统中的广播网络和中继网络的条件接收信号。

95. 发明授权

US07137060B2 Forward error correction apparatus and method in a high-speed data transmission system 有权
标题翻译：高速数据传输系统中的前向纠错装置和方法
公开(公告)号：US07137060B2
公开(公告)日：2006-11-14
申请号：US10458204
申请日：2003-06-11
申请人： Nam-Yul Yu , Min-Goo Kim
发明人： Nam-Yul Yu , Min-Goo Kim
IPC分类号： H03M13/03 , H03M13/00
CPC分类号： H03M13/658 , H03M13/1111 , H03M13/1117 , H03M13/112
摘要： A forward error correction method for decoding coded bits generated by low density parity check matrixes. The method comprises converting each of the coded bits into a log likelihood ratio (LLR) value, and applying the converted values to variable nodes; delivering messages applied to the variable nodes to check nodes; checking a message having a minimum value among the messages, and determining a sign of the message having the minimum value; receiving messages updated in the check nodes, adding up signs of the received messages and a sign of an initial message, applying a weighting factor of 1 when all signs are identical, and when all signs are not identical, updating a message of a variable node by applying a weighting factor; determining LLR of an initial input value; and hard-deciding values of the variable nodes, performing parity check on the hard decision values, and stopping the decoding when no error occurs.
摘要翻译：一种用于解码由低密度奇偶校验矩阵产生的编码比特的前向纠错方法。该方法包括将每个编码比特转换成对数似然比（LLR）值，并将转换的值应用于可变节点; 传递应用于变量节点的消息以检查节点; 检查消息中具有最小值的消息，并确定具有最小值的消息的符号; 接收在校验节点中更新的消息，将接收到的消息的符号和初始消息的符号相加，当所有符号相同时应用加权因子1，并且当所有符号不相同时，更新变量节点的消息通过应用加权因子; 确定初始输入值的LLR; 可变节点的硬判定值，硬判决值进行奇偶校验，无错误发生时停止解码。

96. 发明申请

US20060223476A1 Antenna selection diversity apparatus and method in a broadband wireless communication system 审中-公开
标题翻译：宽带无线通信系统中的天线选择分集装置及方法
公开(公告)号：US20060223476A1
公开(公告)日：2006-10-05
申请号：US11392899
申请日：2006-03-30
申请人： Seong-Wook Song , Young-Mo Gu , Yong-Chul Song , Min-Goo Kim
发明人： Seong-Wook Song , Young-Mo Gu , Yong-Chul Song , Min-Goo Kim
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H04B7/0811
摘要： An apparatus and method for improving antenna diversity in a receiver of a broadband wireless communication system using multiple antennas are provided. The receiver with the diversity apparatus uses a structure of multiple analog front ends, a structure for measuring antenna-by-antenna reception power values/Carrier-to-Interference plus Noise Ratios (CINRs) after Fast Fourier Transform (FFT) using a single analog front end, and a structure based on a single analog front end for measuring antenna-by-antenna reception power values after Analog-to-Digital (A/D) conversion without use of FFT. When a receive antenna is selected, the measured reception power values/CINRs are used. In a system for transmitting pilot signals with preamble data in a regular pattern, the receiver can have improved performance through a suitable frequency modulation process and can be implemented at low cost, as compared with that of the conventional antenna selection diversity.
摘要翻译：提供一种用于改善使用多个天线的宽带无线通信系统的接收机中的天线分集的装置和方法。具有分集装置的接收机使用多个模拟前端的结构，用于使用单个模拟器在快速傅里叶变换（FFT）之后测量天线天线接收功率值/载波与干扰加噪声比（CINR）的结构前端，以及基于单个模拟前端的结构，用于在不使用FFT的情况下测量模数（A / D）转换之后的天线接收功率值。当选择接收天线时，使用测量的接收功率值/ CINR。在用于以规则模式发送具有前导码数据的导频信号的系统中，与常规天线选择分集相比，接收机可以通过适当的频率调制过程具有改进的性能，并且可以以低成本实现。

97. 发明申请

US20060156183A1 Method and apparatus for generating a low-density parity check code 有权
公开(公告)号：US20060156183A1
公开(公告)日：2006-07-13
申请号：US11289300
申请日：2005-11-30
申请人： Sang-Hyo Kim , Han-Ju Kim , Min-Goo Kim , Young-Mo Gu
发明人： Sang-Hyo Kim , Han-Ju Kim , Min-Goo Kim , Young-Mo Gu
IPC分类号： H03M13/00
CPC分类号： H03M13/6362 , H03M13/116 , H03M13/118 , H03M13/1185 , H03M13/1188
摘要： A low density parity check (LDPC) code generating method and apparatus are provided. A parity check matrix with (N−K) rows for check nodes and N columns for variable nodes are formed to encode an information sequence of length K to a codeword of length N. The parity check matrix is divided into an information part matrix with K columns and a parity part matrix with (N−k) columns. The parity part is divided into P×P subblocks. P is a divisor of (N−K). First and second diagonals are defined in the parity part matrix and the second diagonal is a shift of the first diagonal by f subblocks. Shifted identity matrices are placed on the first and second diagonals and zero matrices are filled elsewhere. An odd number of delta matrices each having only one element of 1 are placed in one subblock column of the parity part matrix. The parity check matrix is stored.

98. 发明申请

US20060085726A1 Apparatus and method for decoding Reed-Solomon code 审中-公开
标题翻译：用于解码里德 - 所罗门码的装置和方法
公开(公告)号：US20060085726A1
公开(公告)日：2006-04-20
申请号：US11239689
申请日：2005-09-30
申请人： Jong-Hun Rhee , Min-goo Kim , Su-Yean Kim
发明人： Jong-Hun Rhee , Min-goo Kim , Su-Yean Kim
IPC分类号： H03M13/00
CPC分类号： H03M13/2927 , H03M13/15 , H03M13/1515 , H03M13/29 , H03M13/2906 , H03M13/3738
摘要： An apparatus for receiving and decoding a double-coded symbol in a communication system using a double coding scheme for encoding a Reed-Solomon (RS)-coded symbol with a predetermined scheme for communication. In the apparatus, an inner decoder receives a frame formed with the double-coded symbols, and primary-decodes the received frame. An RS decoding buffer stores an output of the inner decoder frame by frame, and an RS decoder reads symbols in the same column from symbols of a frame stored in the RS decoding buffer, performs RS decoding on the read symbols, and generates an RS decodable indicator value for each symbol. A log likelihood ratio (LLR) update unit updates an LLR value using the RS decodable indicator value, and outputs the updated LLR value to the inner decoder.
摘要翻译：一种用于在通信系统中使用双编码方案来接收和解码双编码符号的装置，所述双重编码方案用于用用于通信的预定方案来编码里德 - 所罗门（RS）编码符号。在该装置中，内部解码器接收由双编码符号形成的帧，并且对接收的帧进行一次解码。 RS解码缓冲器逐帧存储内部解码器的输出，RS解码器从存储在RS解码缓冲器中的帧的符号中读取同一列中的符号，对读取的符号执行RS解码，并生成RS可解码每个符号的指标值。对数似然比（LLR）更新单元使用RS可解码指示符值更新LLR值，并将更新的LLR值输出到内部解码器。

99. 发明申请

US20050271026A1 Method and apparatus for detecting a cell in an orthogonal frequency division multiple access system 有权
标题翻译：用于检测正交频分多址系统中的小区的方法和装置
公开(公告)号：US20050271026A1
公开(公告)日：2005-12-08
申请号：US11108071
申请日：2005-04-18
申请人： Seong-Wook Song , Young-Mo Gu , Min-Goo Kim
发明人： Seong-Wook Song , Young-Mo Gu , Min-Goo Kim
IPC分类号： H04L27/26 , H04B7/216 , H04J11/00 , H04L5/02
CPC分类号： H04B1/7083 , H04L5/0016 , H04L25/0216 , H04L27/2647
摘要： An apparatus and method are provided for detecting via a mobile station a cell in which the mobile station is located in order to initiate communication in an Orthogonal Frequency Division Multiple Access (OFDMA) system including a plurality of base stations transmitting signal with a pseudo-random noise (PN) code to the mobile station. The apparatus and method include receiving the signal from the base station and performing fast Fourier transform (FFT) on the received signal; generating a PN code for comparison with a base station's PN code included in the signal; and detecting a cell where the mobile station is located by searching for a PN code synchronized in the FFT-processed signal using the generated PN code.
摘要翻译：提供了一种装置和方法，用于经由移动台检测移动台所在的小区，以便在包括多个基站的正交频分多址（OFDMA）系统中发起通信，所述正交频分多址（OFDMA）系统发送具有伪随机信号的信号噪声（PN）码到移动台。该装置和方法包括从基站接收信号并对接收到的信号执行快速傅里叶变换（FFT）; 生成用于与包括在信号中的基站的PN码进行比较的PN码; 以及使用所生成的PN码，通过搜索在经FFT处理的信号中同步的PN码来检测移动站所在的小区。

100. 发明申请

US20050262420A1 Apparatus and method for decoding low density parity check codes 有权
标题翻译：解码低密度奇偶校验码的装置和方法
公开(公告)号：US20050262420A1
公开(公告)日：2005-11-24
申请号：US11133287
申请日：2005-05-20
申请人： Sung-Jin Park , Min-Goo Kim , Nam Yu , Han-Ju Kim
发明人： Sung-Jin Park , Min-Goo Kim , Nam Yu , Han-Ju Kim
IPC分类号： H04L27/18 , H03M13/00 , H03M13/11
CPC分类号： H03M13/6566 , H03M13/1137
摘要： An apparatus and method for decoding low density parity check (LDPC) codes are provided. A memory module configured by a plurality of unit memories stores a reliability value. Variable node processors perform a computation associated with a variable node, and update data of the memory module in a column direction, respectively. Check node processors perform a computation associated with a check node, and update data of the memory module in a row direction, respectively. A parity checker determines if all errors have been corrected such that an iterative decoding process is performed. A memory access control module selects a unit memory to be updated by a variable node processor or a check node processor.
摘要翻译：提供了一种用于解码低密度奇偶校验（LDPC）码的装置和方法。由多个单元存储器构成的存储器模块存储可靠性值。可变节点处理器执行与变量节点相关联的计算，并且分别在列方向上更新存储器模块的数据。检查节点处理器执行与校验节点相关联的计算，并分别更新存储器模块在行方向上的数据。奇偶校验器确定所有错误是否已经被校正，使得执行迭代解码过程。存储器访问控制模块选择要由可变节点处理器或校验节点处理器更新的单元存储器。

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