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91. 发明申请

US20140036590A1 PARTIAL BLOCK MEMORY OPERATIONS 审中-公开
标题翻译：部分块存储器操作
公开(公告)号：US20140036590A1
公开(公告)日：2014-02-06
申请号：US13564458
申请日：2012-08-01
申请人： Peter Sean Feeley , Koji Sakui , Akira Goda
发明人： Peter Sean Feeley , Koji Sakui , Akira Goda
IPC分类号： G11C16/04
摘要： Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.
摘要翻译：公开了诸如包括包含电荷存储装置串的存储器单元块的方法和装置。每个串可以包括以多层形成的多个电荷存储装置。该装置可以包括由串共享的多个接入线。多个接入线路中的每一个可以耦合到与多个层级的相应层对应的电荷存储装置。该装置可以包括与弦相关联的多个子源。多个子源中的每一个可以耦合到字符串的多个子集的相应子集的每个串的源选择门，并且每个子源可以独立地从其他子源中选择以选择字符串独立于对应于其他子集的其他字符串。

92. 发明授权

US08638607B2 Disturb verify for programming memory cells 有权
标题翻译：对编程存储单元进行干扰验证
公开(公告)号：US08638607B2
公开(公告)日：2014-01-28
申请号：US13267602
申请日：2011-10-06
申请人： Karthik Sarpatwari , Akira Goda
发明人： Karthik Sarpatwari , Akira Goda
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3454
摘要： Apparatuses and methods for disturb verify for programming operations are described. Programming memory cells can include applying a number of programming pulses to a first memory cell, performing a disturb verify operation on a second memory cell adjacent to the first memory cell, and inhibiting the first memory cell from further programming in response to the second memory cell failing the disturb verify operation. Other apparatuses and methods are also disclosed.
摘要翻译：描述用于编程操作的干扰校验的装置和方法。编程存储器单元可以包括将多个编程脉冲施加到第一存储器单元，对与第一存储器单元相邻的第二存储单元执行干扰校验操作，以及响应于第二存储器单元禁止第一存储器单元进一步编程无法进行干扰验证操作。还公开了其它装置和方法。

93. 发明授权

US08559231B2 Sense operation in a stacked memory array device 有权
标题翻译：堆叠式存储器阵列器件中的检测操作
公开(公告)号：US08559231B2
公开(公告)日：2013-10-15
申请号：US13043005
申请日：2011-03-08
申请人： Akira Goda , Zengtao Liu
发明人： Akira Goda , Zengtao Liu
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C5/02 , G11C5/025 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/28
摘要： One method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers). In one embodiment, the target threshold voltage range can be shifted lower for a slower programming layer. This might be accomplished by biasing the bit lines of slower programming layers with higher bit line voltages as compared to bit line voltages of faster programming layers.
摘要翻译：用于感测的一种方法包括响应于该特定层的编程速率（例如，相对于其它层）改变特定层的感测条件。在一个实施例中，对于较慢的编程层，目标阈值电压范围可以更低。与较快编程层的位线电压相比，可以通过将较慢编程层的位线与较高位线电压相比较来实现。

94. 发明授权

US08514620B2 Memory devices having select gates with P type bodies, memory strings having separate source lines and methods 有权
标题翻译：具有带有P型体的选择栅极的存储器件，具有分离的源极线的存储器串和方法
公开(公告)号：US08514620B2
公开(公告)日：2013-08-20
申请号：US12955448
申请日：2010-11-29
申请人： Akira Goda
发明人： Akira Goda
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C7/00 , G11C16/0466 , G11C16/10 , G11C16/26 , H01L27/115 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/78 , H01L29/7889 , H01L29/7926
摘要： Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.
摘要翻译：显示了存储器件和操作存储器件的方法。所描述的配置包括具有细长n型体区并且具有p型体的选择栅的存储单元串。所示的配置和方法可以为身体区域提供可靠的偏置，用于诸如擦除的存储器操作。

95. 发明授权

US08406047B2 Memory devices having select gates with P type bodies, memory strings having separate source lines and methods 有权
公开(公告)号：US08406047B2
公开(公告)日：2013-03-26
申请号：US12955448
申请日：2010-11-29
申请人： Akira Goda
发明人： Akira Goda
IPC分类号： G11C11/34
摘要： Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.

96. 发明申请

US20120230116A1 SENSE OPERATION IN A STACKED MEMORY ARRAY DEVICE 有权
标题翻译：堆栈存储器阵列设备中的感知操作
公开(公告)号：US20120230116A1
公开(公告)日：2012-09-13
申请号：US13043005
申请日：2011-03-08
申请人： Akira Goda , Zengtao Liu
发明人： Akira Goda , Zengtao Liu
IPC分类号： G11C16/06 , G11C16/26
CPC分类号： G11C16/10 , G11C5/02 , G11C5/025 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/28
摘要： Methods for sensing and memory devices are disclosed. One such method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers).
摘要翻译：公开了用于感测和存储器件的方法。用于感测的一种这样的方法包括响应于该特定层的编程速率（例如，相对于其他层）改变特定层的感测条件。

97. 发明申请

US20120113713A1 Methods of Operating a Memory Device Having a Buried Boosting Plate 有权
标题翻译：操作具有埋藏升压板的存储器件的方法
公开(公告)号：US20120113713A1
公开(公告)日：2012-05-10
申请号：US13351148
申请日：2012-01-16
申请人： Akira Goda
发明人： Akira Goda
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , H01L21/84 , H01L27/11526 , H01L27/11529 , H01L27/1203
摘要： Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.
摘要翻译：公开了存储器件，诸如包括具有升压板的绝缘体上半导体（SOI）NAND存储器阵列的存储器件。升压板可以设置在SOI衬底的绝缘体层中，使得升压板对存储器阵列的p阱施加电容耦合效应。这种升压板可用于在存储器阵列的编程和擦除操作期间升压p阱。在读取操作期间，升压板可以接地以最小化与p阱的相互作用。还公开了包括存储器阵列的系统和操作存储器阵列的方法。

98. 发明申请

US20110128782A1 REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE 有权
标题翻译：减少存储器件中擦除干扰的影响
公开(公告)号：US20110128782A1
公开(公告)日：2011-06-02
申请号：US12628522
申请日：2009-12-01
申请人： Akira Goda , Alessandro Torsi , Carlo Musilli , Mark A. Helm , Doyle Rivers
发明人： Akira Goda , Alessandro Torsi , Carlo Musilli , Mark A. Helm , Doyle Rivers
IPC分类号： G11C7/00 , G11C16/10
CPC分类号： G11C16/3418 , G11C16/0483 , G11C16/14
摘要： Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.
摘要翻译：公开了用于编程和存储器件的方法。一种用于编程的方法包括：初始地利用负电压偏置存储器单元串的多个控制栅极的子集，其中该子集小于该串的多个控制栅极的全部。在编程阶段期间，所选择的存储单元的控制栅随后用编程电压进行偏置。

99. 发明申请

US20100128529A1 NAND STEP VOLTAGE SWITCHING METHOD 有权
标题翻译： NAND步进电压开关方式
公开(公告)号：US20100128529A1
公开(公告)日：2010-05-27
申请号：US12696279
申请日：2010-01-29
申请人： Akira Goda , Taehoon Kim , Doyle Rivers , Roger Porter
发明人： Akira Goda , Taehoon Kim , Doyle Rivers , Roger Porter
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C5/145 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621
摘要： Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.
摘要翻译：具有用于根据正在编程的多电平单元的电平改变Vstep增量的切换点的方法和存储器包括在窄阈值电压情况下以较小的Vstep增量进行编程，并且在需要更快编程的较大Vstep增量下进行编程。

100. 发明申请

US20100052032A1 Nonvolatile semiconductor memory and method for fabricating the same 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20100052032A1
公开(公告)日：2010-03-04
申请号：US12588203
申请日：2009-10-07
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

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