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91. 发明授权

US09152581B2 Chip storing a value that represents adjustment to output drive strength 有权
标题翻译：芯片存储表示调整输出驱动强度的值
公开(公告)号：US09152581B2
公开(公告)日：2015-10-06
申请号：US14686522
申请日：2015-04-14
申请人： Rambus Inc.
发明人： Mark A. Horowitz , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/40 , G06F13/10 , G06F13/42 , G11C5/04 , G11C5/06 , G11C7/10 , H03K19/003 , H03K19/0185 , G11C19/00 , G06F3/06 , G06F13/16 , G06F13/364 , G06F12/10 , G11C16/32 , G11C7/22
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.
摘要翻译：集成电路装置包括具有输出驱动器的发送器电路。集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

92. 发明申请

US20150229468A1 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 有权
标题翻译：通信通道校准条件
公开(公告)号：US20150229468A1
公开(公告)日：2015-08-13
申请号：US14695597
申请日：2015-04-24
申请人： Rambus Inc.
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC分类号： H04L7/00
CPC分类号： H04L7/0016 , G11C7/04 , G11C2207/2254 , H04L7/0087 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/0292 , H04L25/12
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
摘要翻译：方法和系统提供在通信信道的正常操作期间不时地执行校准周期。校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。使用第二组件上的接收器从通信链路接收校准模式。响应于所接收的校准模式来确定通信信道的参数的校准值。校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，并将这些校准模式重新发送回第一组件，以用于调整第一组件上的通道的参数。

93. 发明申请

US20150220270A1 CHIP STORING A VALUE THAT REPRESENTS ADJUSTMENT TO OUTPUT DRIVE STRENGTH 有权
标题翻译：芯片存储一个代表调整输出驱动强度的值
公开(公告)号：US20150220270A1
公开(公告)日：2015-08-06
申请号：US14686522
申请日：2015-04-14
申请人： Rambus Inc.
发明人： Mark A. Horowitz , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F3/06 , G06F13/364
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.
摘要翻译：集成电路装置包括具有输出驱动器的发送器电路。集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

94. 发明申请

US20150212968A1 CHIP HAVING PORT TO RECEIVE VALUE THAT REPRESENTS ADJUSTMENT TO OUTPUT DRIVER PARAMETER 有权
标题翻译：具有端口接收输出驱动器参数的值的芯片
公开(公告)号：US20150212968A1
公开(公告)日：2015-07-30
申请号：US14683290
申请日：2015-04-10
申请人： Rambus Inc.
发明人： Mark A. Horowitz , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/40 , G06F13/42 , G06F13/364
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.
摘要翻译：集成电路装置包括具有输出驱动器的发送器电路。集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

95. 发明申请

US20150212954A1 CHIP HAVING PORT TO RECEIVE VALUE THAT REPRESENTS ADJUSTMENT TO TRANSMISSION PARAMETER 有权
标题翻译：接收端口接收传输参数调整值的芯片
公开(公告)号：US20150212954A1
公开(公告)日：2015-07-30
申请号：US14682926
申请日：2015-04-09
申请人： Rambus Inc.
发明人： Mark A. Horowitz , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/16 , G06F3/06 , G06F13/364
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.
摘要翻译：集成电路装置包括具有输出驱动器的发送器电路。集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

96. 发明申请

US20150043290A1 MEMORY MODULE 有权
标题翻译：记忆模块
公开(公告)号：US20150043290A1
公开(公告)日：2015-02-12
申请号：US14523922
申请日：2014-10-26
申请人： Rambus Inc.
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C7/22 , G11C11/409
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective IC components, and the address/control signal path and clock signal path are coupled in common to all the IC components. The address/control signal path extends along the IC components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components.
摘要翻译：具有集成电路（IC）组件，终端结构，地址/控制信号路径，时钟信号路径，多个数据信号路径和多个选通信号路径的存储模块。选通信号路径和数据信号路径耦合到相应的IC组件，并且地址/控制信号路径和时钟信号路径共同耦合到所有IC组件。地址/控制信号路径沿着IC组件延伸到终端结构，使得朝向终端结构传播的控制信号在对应于IC组件的相对位置的逐渐更新的时间到达各个IC组件的地址/控制输入。

97. 发明申请

US20150023118A1 RECONFIGURABLE MEMORY SYSTEM DATA STROBES 有权
标题翻译：可重构存储器系统数据条
公开(公告)号：US20150023118A1
公开(公告)日：2015-01-22
申请号：US14509572
申请日：2014-10-08
申请人： RAMBUS INC.
发明人： Ian Shaeffer , Frederick Ware , Craig E. Hampel
IPC分类号： G06F3/06 , G11C7/22
CPC分类号： G06F3/0634 , G06F3/0665 , G06F3/0689 , G06F13/1694 , G06F2212/262 , G11C7/22
摘要： In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of the components of the differential data strobe may be used as a timing reference for a first portion of the set of data signals and the other component used as a timing reference for a second portion of the set of data signals. Different data mask-related schemes also may be invoked for different modes of operation. For example, in a first mode of operation a memory controller may generate a data mask signal to prevent a portion of a set of data from being written to a memory array. Then, in a second mode of operation the memory controller may invoke a coded value replacement scheme or a data strobe transition inhibition scheme to prevent a portion of a set of data from being written to a memory array.
摘要翻译：在可重新配置的基于数据选通的存储器系统中，数据选通可以在不同的操作模式下重新安排。例如，在一种操作模式中，差分数据选通可以用作给定的一组数据信号的定时参考。在第二操作模式中，可以将差分数据选通的一个组件用作数据信号组的第一部分的定时参考，另一组件用作该组数据信号的第二部分的定时参考数据信号。也可以针对不同的操作模式调用不同的数据掩码相关方案。例如，在第一操作模式中，存储器控制器可以生成数据掩码信号以防止一组数据被写入存储器阵列。然后，在第二操作模式中，存储器控制器可以调用编码值替换方案或数据选通转换禁止方案，以防止一组数据被写入存储器阵列。

98. 发明申请

US20150019786A1 METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULES 有权
标题翻译：用于同步在线程存储器模块中的地址和控制信号的方法和系统
公开(公告)号：US20150019786A1
公开(公告)日：2015-01-15
申请号：US14284473
申请日：2014-05-22
申请人： RAMBUS INC.
发明人： Arun Vaidyanath , Craig E. Hampel
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F13/16 , G06F12/06 , G06F13/1689 , G06F2212/251 , G11C5/04 , G11C5/063 , G11C7/1072 , G11C8/18 , G11C29/023 , G11C29/025 , G11C29/027
摘要： A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time.
摘要翻译：存储器系统包括还包括一组存储器件的存储器模块。该组存储器件包括存储器件的第一子集和存储器件的第二子集。地址总线设置在存储器模块上，其中地址总线包括耦合到第一子集的第一段和耦合到第二子集的第二段。地址信号依次遍历该组存储器件。存储器系统还包括耦合到存储器模块的存储器控制器。存储器控制器包括第一电路，用于输出控制第一子集的第一控制信号，使得第一控制信号和地址信号在基本上同时到达第一子集中的存储器件。存储器控制器还包括第二电路，用于输出控制第二子集的第二控制信号，使得第二控制信号和地址信号在基本上同时到达第二子集中的存储器件。

99. 发明申请

US20150006771A1 Chip Having Register to Store Value that Represents Adjustment to Reference Voltage 有权
标题翻译：芯片有注册存储代表调整参考电压的值
公开(公告)号：US20150006771A1
公开(公告)日：2015-01-01
申请号：US14321718
申请日：2014-07-01
申请人： Rambus Inc.
发明人： Mark A. Horowitz , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/10
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.
摘要翻译：集成电路装置包括具有输出驱动器的发送器电路。集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

100. 发明授权

US08769234B2 Memory modules and devices supporting configurable data widths 有权
标题翻译：支持可配置数据宽度的内存模块和设备
公开(公告)号：US08769234B2
公开(公告)日：2014-07-01
申请号：US13778534
申请日：2013-02-27
申请人： Rambus Inc.
发明人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/00
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations.
摘要翻译：描述了组织在物理存储体中的存储装置，并且包括可配置数据控制电路以支持多个数据宽度配置。相对窄的宽度配置加载较少的读出放大器，导致相对较窄的存储器配置的功率消耗减少。还描述了将配置值传递给可配置存储器设备并且支持多个宽度配置的点对点数据缓冲器的存储器控制器。

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