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91. 发明授权

US06888370B1 Dynamically adjustable termination impedance control techniques 有权
标题翻译：动态可调终端阻抗控制技术
公开(公告)号：US06888370B1
公开(公告)日：2005-05-03
申请号：US10645932
申请日：2003-08-20
申请人： Mei Luo , Wilson Wong , Sergey Shumarayev
发明人： Mei Luo , Wilson Wong , Sergey Shumarayev
IPC分类号： H03K19/0175 , H04L25/02
CPC分类号： H04L25/0278
摘要： The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.
摘要翻译：片内阻抗终端电路可以动态调节，以匹配传输线阻抗值。集成电路上的终端电阻网络为耦合到IO引脚的传输线提供终端阻抗。终端电阻器串联耦合并且彼此并联。通孔与电阻耦合。传递门单独接通或断开以将电阻与传输线耦合或去耦。每个通过门被设置为ON或OFF以向传输线提供所选择的终端电阻值。可以增加或减少电阻网络的终端电阻以匹配不同传输线路的阻抗。也可以改变终端电阻以补偿由集成电路上的温度变化或其他因素引起的电阻器的变化。

92. 发明授权

US08385496B1 Apparatus and methods of receiver offset calibration 有权
标题翻译：接收机偏移校准的装置和方法
公开(公告)号：US08385496B1
公开(公告)日：2013-02-26
申请号：US12909744
申请日：2010-10-21
申请人： Allen Chan , Wilson Wong , Sergey Shumarayev
发明人： Allen Chan , Wilson Wong , Sergey Shumarayev
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04L7/033
摘要： One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.
摘要翻译：一个实施例涉及一种用于集成电路中的接收机的偏移抵消的方法。接收机设置为相位检测器偏移消除模式，以便确定相位检测器的偏移消除设置。偏移消除设置被应用于相位检测器。然后将接收机设置为接收器 - 驱动器偏移消除模式，以便确定接收器驱动器的偏移消除设置。该偏移消除设置被应用于接收器驱动器。另一实施例涉及被配置为执行接收机偏移消除的集成电路。该集成电路包括被配置为接收差分输入信号的接收器驱动器，包括多个锁存器的相位检测器，校准控制器，电压源以及第一和第二对开关。还公开了其它实施例，方面和特征。

93. 发明授权

US08319564B2 Integrated circuits with configurable inductors 有权
标题翻译：具有可配置电感器的集成电路
公开(公告)号：US08319564B2
公开(公告)日：2012-11-27
申请号：US12748261
申请日：2010-03-26
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H03B5/12 , H03L1/00
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

94. 发明授权

US08194724B1 Adaptive equalization methods and apparatus for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的自适应均衡方法和装置
公开(公告)号：US08194724B1
公开(公告)日：2012-06-05
申请号：US12823783
申请日：2010-06-25
申请人： Wilson Wong , Sergey Shumarayev , Simardeep Maangat , Rakesh Patel
发明人： Wilson Wong , Sergey Shumarayev , Simardeep Maangat , Rakesh Patel
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L25/03044 , H04L2025/03356 , H04L2025/03579 , H04L2025/03783
摘要： A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.
摘要翻译：可编程逻辑器件设置有可在一个或多个方面可编程的自适应均衡电路。均衡电路的可编程方面的示例是（1）使用的抽头数量，（2）是否使用整数或分数间隔抽头，（3）在系数值的计算中使用什么起始值，（4）是否（5）是否使用决策导向算法或使用训练模式生成错误信号，（6）使用何种训练模式（如果有的话）和/ 或者（7）要被均衡的信号的位周期内的采样点的位置。

95. 发明申请

US20110234331A1 INTEGRATED CIRCUITS WITH CONFIGURABLE INDUCTORS 有权
标题翻译：集成电路与配置电感器
公开(公告)号：US20110234331A1
公开(公告)日：2011-09-29
申请号：US12748261
申请日：2010-03-26
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H03B5/12 , H01F5/00
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

96. 发明申请

US20100058099A1 HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的宽范围可编程性的异构收发器架构
公开(公告)号：US20100058099A1
公开(公告)日：2010-03-04
申请号：US12576507
申请日：2009-10-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

97. 发明申请

US20090284292A1 SIGNAL ADJUSTMENT RECEIVER CIRCUITRY 审中-公开
公开(公告)号：US20090284292A1
公开(公告)日：2009-11-19
申请号：US12511024
申请日：2009-07-28
申请人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
发明人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
IPC分类号： H03K5/12
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

98. 发明申请

US20090257445A1 PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION 有权
标题翻译：针对10G以太网物理层解决方案优化的PLD架构
公开(公告)号：US20090257445A1
公开(公告)日：2009-10-15
申请号：US12100360
申请日：2008-04-09
申请人： Allen Chan , Sergey Shumarayev , Wilson Wong , Weiqi Ding
发明人： Allen Chan , Sergey Shumarayev , Wilson Wong , Weiqi Ding
IPC分类号： H04L12/66
CPC分类号： H04L49/30 , H04L49/352
摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.
摘要翻译：集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

99. 发明授权

US07541857B1 Comparator offset cancellation assisted by PLD resources 有权
标题翻译：比较器偏移消除由PLD资源辅助
公开(公告)号：US07541857B1
公开(公告)日：2009-06-02
申请号：US11323571
申请日：2005-12-29
申请人： Wilson Wong , Tin H. Lai , Sergey Shumarayev , Rakesh H. Patel
发明人： Wilson Wong , Tin H. Lai , Sergey Shumarayev , Rakesh H. Patel
IPC分类号： H03L5/00
CPC分类号： H03F3/45183 , H03F3/45632 , H03F2203/45212 , H03F2203/45646 , H03F2203/45681 , H03F2203/45702 , H03F2203/45726
摘要： An impedance compensation circuit for inputs of a programmable device includes programmable impedance circuits connected with input nodes. The programmable impedance circuits can be configured to apply a compensating voltages to input nodes to reduce or eliminate unwanted offset voltages. An impedance compensation circuit may include resistors in series or current sources in parallel. A set of bypass switches selectively apply each resistor or current source to an input node, thereby changing the offset voltage of the node and compensating for impedance mismatches. Control logic provides signals to control the bypass switches. The control logic may be implemented using programmable device resources, enabling the control logic to be updated and improved after the manufacturing of the device is complete. The control logic can automatically evaluate offset voltages at any time and change compensating impedances accordingly. This reduces manufacturing costs and takes into account temperature and aging effects.
摘要翻译：用于可编程器件的输入的阻抗补偿电路包括与输入节点连接的可编程阻抗电路。可编程阻抗电路可以配置为向输入节点施加补偿电压以减少或消除不期望的失调电压。阻抗补偿电路可以包括并联的串联或电流源的电阻器。一组旁路开关选择性地将每个电阻器或电流源施加到输入节点，从而改变节点的偏移电压并补偿阻抗失配。控制逻辑提供信号来控制旁路开关。可以使用可编程设备资源实现控制逻辑，使得在设备的制造完成之后能够更新和改进控制逻辑。控制逻辑可以随时自动评估偏移电压，并相应地改变补偿阻抗。这降低了制造成本并考虑了温度和老化的影响。

100. 发明授权

US07492816B1 Adaptive equalization methods and apparatus 失效
标题翻译：自适应均衡方法和装置
公开(公告)号：US07492816B1
公开(公告)日：2009-02-17
申请号：US10853987
申请日：2004-05-25
申请人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
发明人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
IPC分类号： H03H7/30
CPC分类号： H04L1/205 , H04B17/21 , H04B17/24 , H04B17/309 , H04L25/03006
摘要： A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e.g., equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.
摘要翻译：系统包括经由用于从发射机向接收机发送高速数据信号的传输介质连接到可编程接收机设备（例如，另一个PLD）的可编程发射机设备（例如，PLD）。在测试操作模式期间，发射机和接收机之间的低速通信链路允许这些设备一起工作，以经由传输介质从发射机向接收机发送具有已知特性的测试信号，以分析由接收器，并且至少部分地补偿由接收器接收的测试信号中的损耗，系统的至少一些方面（例如，接收机中的均衡器电路）。

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