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91. 发明申请

US20070140387A1 Signal adjustment receiver circuitry 有权
标题翻译：信号调节接收器电路
公开(公告)号：US20070140387A1
公开(公告)日：2007-06-21
申请号：US11312181
申请日：2005-12-20
申请人： Wilson Wong , Rakesh Patel , Sergey Shumarayev , Tin Lai
发明人： Wilson Wong , Rakesh Patel , Sergey Shumarayev , Tin Lai
IPC分类号： H04L27/06
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
摘要翻译：公开了一种用于调整从通信路径接收的信号的系统和方法。接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。对于低频调整，控制块控制信号归一化块中的归一化信号幅度。以这种方式，在信号归一化块中执行低频内容的受控调整。

92. 发明申请

US20070041455A1 High-speed serial data receiver architecture 有权
标题翻译：高速串行数据接收机架构
公开(公告)号：US20070041455A1
公开(公告)日：2007-02-22
申请号：US11361192
申请日：2006-02-23
申请人： Thungoc Tran , Sergey Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
发明人： Thungoc Tran , Sergey Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
IPC分类号： H04L25/00
CPC分类号： H04L1/243 , H04L25/03878
摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
摘要翻译：用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。接收器电路的控制的各个方面可以是可编程的。

93. 发明授权

US07135885B2 Dynamically adjustable signal detector 有权
标题翻译：动态可调信号检测器
公开(公告)号：US07135885B2
公开(公告)日：2006-11-14
申请号：US11270229
申请日：2005-11-08
申请人： Wilson Wong , Sergey Shumarayev
发明人： Wilson Wong , Sergey Shumarayev
IPC分类号： H03K19/03
CPC分类号： G01R31/31932 , G01R31/3167 , H03K5/1252 , H03K19/003 , H04L25/0292
摘要： A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, peak power, average power, or other suitable settings, and can have a dynamically adjustable value for a selected threshold setting. The threshold settings and the value for a selected threshold setting can be set using control signals that are set by programmable logic resource circuitry, by soft intellectual property programmed into a programmable logic resource, by a processor, by circuitry external to a programmable logic resource, or by user input.
摘要翻译：动态可调信号检测器接收差分输入信号，并且基于动态可调的阈值设置输出表示是否正在接收有效信号的信号。阈值设置可以包括差分电压，峰值功率，平均功率或其他适当的设置，并且可以为所选阈值设置具有动态可调整的值。可以使用由可编程逻辑资源电路设置的控制信号，通过编程到可编程逻辑资源中的软知识产权，由处理器，可编程逻辑资源外部的电路设置阈值设置和值，或用户输入。

94. 发明申请

US20060165204A1 Method and apparatus for multi-mode clock data recovery 失效
公开(公告)号：US20060165204A1
公开(公告)日：2006-07-27
申请号：US11040342
申请日：2005-01-21
申请人： Sergey Shumarayev , Rakesh Patel , Wilson Wong , Tim Hoang
发明人： Sergey Shumarayev , Rakesh Patel , Wilson Wong , Tim Hoang
IPC分类号： H04L7/00 , H03D3/24
CPC分类号： H03L7/0998 , H03L7/081 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/0025 , H04L7/0083 , H04L7/033
摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.

95. 发明申请

US20060066347A1 Dynamically adjustable signal detector 有权
公开(公告)号：US20060066347A1
公开(公告)日：2006-03-30
申请号：US11270229
申请日：2005-11-08
申请人： Wilson Wong , Sergey Shumarayev
发明人： Wilson Wong , Sergey Shumarayev
IPC分类号： H03K19/003
CPC分类号： G01R31/31932 , G01R31/3167 , H03K5/1252 , H03K19/003 , H04L25/0292
摘要： A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, peak power, average power, or other suitable settings, and can have a dynamically adjustable value for a selected threshold setting. The threshold settings and the value for a selected threshold setting can be set using control signals that are set by programmable logic resource circuitry, by soft intellectual property programmed into a programmable logic resource, by a processor, by circuitry external to a programmable logic resource, or by user input.

96. 发明申请

US20050237082A1 Integrated circuit output driver circuitry with programmable preemphasis 有权
公开(公告)号：US20050237082A1
公开(公告)日：2005-10-27
申请号：US11148046
申请日：2005-06-07
申请人： Sergey Shumarayev , Thomas White , Rakesh Patel , Wilson Wong
发明人： Sergey Shumarayev , Thomas White , Rakesh Patel , Wilson Wong
IPC分类号： H03K19/0185 , H03K19/177 , H04L25/02 , H03K19/003
CPC分类号： H03K19/17744 , H03K19/018585 , H03K19/1778 , H04L25/0272 , H04L25/0286
摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

97. 发明授权

US06943588B1 Dynamically-adjustable differential output drivers 有权
标题翻译：动态可调差分输出驱动器
公开(公告)号：US06943588B1
公开(公告)日：2005-09-13
申请号：US10670146
申请日：2003-09-24
申请人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
发明人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
IPC分类号： H03K19/094
CPC分类号： H03K19/00369 , H03K19/01812 , H03K19/01837 , H03K19/018514 , H03K19/018585
摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.
摘要翻译：使用动态可调差分输出驱动器提供系统和方法。诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。可以调整输出驱动器的峰峰值输出电压和共模电压。动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

98. 发明授权

US08976804B1 Power supply filtering for programmable logic device having heterogeneous serial interface architecture 有权
标题翻译：具有异构串行接口架构的可编程逻辑器件的电源滤波
公开(公告)号：US08976804B1
公开(公告)日：2015-03-10
申请号：US13041764
申请日：2011-03-07
申请人： Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04L12/66
CPC分类号： H03K19/17744
摘要： In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.
摘要翻译：在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

99. 发明授权

US08385496B1 Apparatus and methods of receiver offset calibration 有权
标题翻译：接收机偏移校准的装置和方法
公开(公告)号：US08385496B1
公开(公告)日：2013-02-26
申请号：US12909744
申请日：2010-10-21
申请人： Allen Chan , Wilson Wong , Sergey Shumarayev
发明人： Allen Chan , Wilson Wong , Sergey Shumarayev
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04L7/033
摘要： One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.
摘要翻译：一个实施例涉及一种用于集成电路中的接收机的偏移抵消的方法。接收机设置为相位检测器偏移消除模式，以便确定相位检测器的偏移消除设置。偏移消除设置被应用于相位检测器。然后将接收机设置为接收器 - 驱动器偏移消除模式，以便确定接收器驱动器的偏移消除设置。该偏移消除设置被应用于接收器驱动器。另一实施例涉及被配置为执行接收机偏移消除的集成电路。该集成电路包括被配置为接收差分输入信号的接收器驱动器，包括多个锁存器的相位检测器，校准控制器，电压源以及第一和第二对开关。还公开了其它实施例，方面和特征。

100. 发明授权

US08319564B2 Integrated circuits with configurable inductors 有权
标题翻译：具有可配置电感器的集成电路
公开(公告)号：US08319564B2
公开(公告)日：2012-11-27
申请号：US12748261
申请日：2010-03-26
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H03B5/12 , H03L1/00
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

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